<?xml version="1.0" encoding="utf-8"?>
<FitData version="10.22" sku="CMP-LP No Emulation" HarnessProject="CMP-LP PCH" HarnessLabel="v0.78 CMP-LP (Harness #77)" HarnessRevision="#77" >
    <BuildSettings label="Build Settings">
        <BuildResults label="Image Build Settings">
            <BuildOutputFilename value="$DestDir\outimage.bin" label="Output Path" />
            <BuildFWUpdateOutputFilename value="$DestDir\FWUpdate.bin" label="FWUpdate Output Path" />
            <BuildFWUpdateWithFullImage value="No" value_list="No,,Yes" label="Build FWUpdate With Full Image" />
            <GenIntermediateFiles value="Yes" value_list="No,,Yes" label="Generate Intermediate Files" />
            <BootGrdWrn value="Yes" value_list="No,,Yes" label="Enable Boot Guard warning message at build time" />
            <PTTWrn value="Yes" value_list="No,,Yes" label="Enable Intel (R) Platform Trust Technology warning message at build time" />
            <RegionOrder value="45321" label="Region Order" help_text="1=BIOS, 2=ME/IFWI, 3=GbE, 4=PDR, 5=EC" />
            <IfwiBuildVersion value="0x0" help_text="32-bit value to use as the IFWI build version number" />
            <IfwiRedundancyEnabled value="true" value_list="true,,false" label="Redundancy Enabled" help_text="Enable Redundancy support for critical layout components" />
            <MeuToolPath value="" label="Intel(R) Manifest Extension Utility Path" />
            <SigningToolPath value="" label="Signing Tool Path" />
            <SigningTool value="OpenSSL" value_list="OpenSSL,,Disabled" label="Signing Tool" />
        </BuildResults>
        <PathVars label="Environment Variables">
            <WorkingDir value="." label="$WorkingDir" help_text="Path for environment variable $WorkingDir" />
            <SourceDir value="." label="$SourceDir" help_text="Path for environment variable $SourceDir" />
            <DestDir value="." label="$DestDir" help_text="Path for environment variable $DestDir" />
            <UserVar1 value="." label="$UserVar1" help_text="Path for environment variable $UserVar1" />
            <UserVar2 value="." label="$UserVar2" help_text="Path for environment variable $UserVar2" />
            <UserVar3 value="." label="$UserVar3" help_text="Path for environment variable $UserVar3" />
        </PathVars>
    </BuildSettings>
    <FlashLayout label="Flash Layout">
        <DescriptorRegion label="Descriptor Region">
            <OemBinary value="D:\Software Programmer Sept 2025\Bios Software\Flash Image Tool\Flash Image Tool 14.0.60.1790\WIN32\20251214_171950_XM25QH256B\Decomp\OemBinary.bin" label="OEM Section Binary" help_text="This loads the OEM Section binary that will be merged into the output image generated by the Intel(R) FIT tool." />
        </DescriptorRegion>
        <BiosRegion label="BIOS Region">
            <Length value="0" label="BIOS Length" />
            <InputFile value="D:\Software Programmer Sept 2025\Bios Software\Flash Image Tool\Flash Image Tool 14.0.60.1790\WIN32\20251214_171950_XM25QH256B\Decomp\BIOS Region.bin" label="BIOS Binary File" help_text="This loads the BIOS binary that will be merged into the output image generated by the Intel (R) FIT tool." />
        </BiosRegion>
        <Ifwi_IntelMePmcRegion label="Ifwi: Intel(R) Me and Pmc Region">
            <MeRegionFile value="D:\Software Programmer Sept 2025\Bios Software\Flash Image Tool\Flash Image Tool 14.0.60.1790\WIN32\20251214_171950_XM25QH256B\Decomp\ME Sub Partition.bin" label="Intel(R) ME Binary File" help_text="This loads the Intel(R) ME binary that will be merged into the output image generated by the Intel(R) FIT tool." />
            <ChipInitBinary value="" label="Chipset Initialization Binary" help_text="This loads the Chipset Initialization binary that will be merged into the output image generated by the Intel(R) FIT tool." />
            <PmcBinary value="D:\Software Programmer Sept 2025\Bios Software\Flash Image Tool\Flash Image Tool 14.0.60.1790\WIN32\20251214_171950_XM25QH256B\Decomp\PMC Region.bin" label="PMC Binary File" help_text="This loads the PMC binary that will be merged into the output image generated by Intel(R) FIT tool." />
            <PmcLength value="0x14000" label="PMC Length" />
            <ResizeNftpForFtpr value="Enabled" value_list="Disabled,,Enabled" label="Enables NFTP resize for FTPR loading" help_text="Used to enable NFTP resize for FTPR loading to perform FWU process. Disable for SKU's and platforms with limited image size, without FWU support only." />
        </Ifwi_IntelMePmcRegion>
        <EcRegion label="EC Region">
            <Length value="0" label="EC Length" />
            <InputFile value="D:\Software Programmer Sept 2025\Bios Software\Flash Image Tool\Flash Image Tool 14.0.60.1790\WIN32\20251214_171950_XM25QH256B\Decomp\EC Region.bin" label="EC Binary File" help_text="This loads the Embedded Controller binary used for eSPI that will be merged into the output image generated by the Intel (R) FIT tool." />
            <Enabled value="Enabled" value_list="Disabled,,Enabled" label="EC Region Enable" help_text="This option allows the user to enable or disable the Embedded Controller Data Region." />
            <EcRegionPointer value="D:\Software Programmer Sept 2025\Bios Software\Flash Image Tool\Flash Image Tool 14.0.60.1790\WIN32\20251214_171950_XM25QH256B\Decomp\EcRegionPointer.bin" label="EC Region Pointer File" help_text="This loads a binary containing the 16 byte value to be written in the Embedded Controller Pointer region." />
        </EcRegion>
        <GbeRegion label="GbE Region">
            <Length value="0" label="GbE Length" />
            <InputFile value="D:\Software Programmer Sept 2025\Bios Software\Flash Image Tool\Flash Image Tool 14.0.60.1790\WIN32\20251214_171950_XM25QH256B\Decomp\GBE Region.bin" label="GbE Binary File" help_text="This loads the Intel(R) Integrated LAN binary that will be merged into the output image generated by the Intel (R) FIT tool." />
            <Enabled value="Enabled" value_list="Disabled,,Enabled" label="GbE Region Enable" help_text="This option allows the user to enable or disable the Gigabit Ethernet Region." />
        </GbeRegion>
        <SubPartitions>
            <IunitSubPartition label="IUnit Sub-Partition">
                <InputFile value="" label="IUnit Binary File" help_text="This loads the IUnit binary that will be merged into the output image generated by Intel(R) FIT tool." />
                <Length value="0xA000" label="Iunit Length" />
            </IunitSubPartition>
            <PchcSubPartitionData label="PCH Configuration Sub-Partition">
                <InputFile value="D:\Software Programmer Sept 2025\Bios Software\Flash Image Tool\Flash Image Tool 14.0.60.1790\WIN32\20251214_171950_XM25QH256B\Decomp\PCH Configuration Region.bin" label="PCH Configuration File" help_text="This loads the PCH Configuration binary that will be merged into the output image generated by Intel(R) FIT tool." />
                <Length value="0x1000" label="PCH Configuration Length" />
            </PchcSubPartitionData>
        </SubPartitions>
        <PdrRegion label="PDR Region">
            <Length value="0" />
            <InputFile value="" label="PDR Binary File" help_text="This loads the Platform Data region binary that will be merged into the output image generated by the Intel (R) FIT tool." />
            <Enabled value="Disabled" value_list="Disabled,,Enabled" label="PDR Region Enable" help_text="This option allows the user to enable or disable the Platform Data Region." />
        </PdrRegion>
    </FlashLayout>
    <FlashSettings label="Flash Settings">
        <FlashComponents label="Flash Components">
            <NumberOfComponents value="1" value_list="0,,1,,2" label="Number of Flash Components" help_text="Specifies the number of Flash components that will be installed on the target machine if using SPI." />
            <FlashComponent1Size value="32MB" value_list="512KB,,1MB,,2MB,,4MB,,8MB,,16MB,,32MB,,64MB" label="Flash component 1 Size" help_text="This field identifies the size of the 1st Flash component." />
            <FlashComponent2Size value="8MB" value_list="512KB,,1MB,,2MB,,4MB,,8MB,,16MB,,32MB,,64MB" label="Flash component 2 Size" help_text="This field identifies the size of the 2nd Flash component." />
            <SpiVoltageSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="SPI Voltage Select" help_text="This strap sets the internal control signal on the pad for either 1.8 or 3.3 V operation.  See Canonlake H / LP SPI Programming guide further details." />
            <SpiGblProtRng value="0x00000000" label="SPI Global Protected Range" help_text="Sets the default value of the Global Protected Range register in the SPI Flash Controller." />
            <SpiIdlDpdwntimeout value="0x00000005" label="SPI Idle to Deep Power Down Timeout" help_text="SPI Idle to Deep Power Down Timeout Default Specifies the time in microseconds that the Flash Controller waits after all activity is idle before commanding the flash devices to Deep Power down, time = 2^N microseconds." />
            <SpiOooEnable value="Yes" value_list="Yes,,No" label="SPI Out of Order operation Enabled" help_text="When this setting is enabled priority operations may be issued while waiting for write / erase operations to complete on the flash device.  When this setting is disabled all write / erase type operations in order." />
            <SpiResHldDelay value="4us" value_list="0us,,2us,,4us,,6us,,8us,,10us,,12us,,14us" label="SPI Resume Hold-off Delay" help_text="Specifies the time after the completion of a pri_op before the flash controller sends the resume instruction. If a new pri_op is eligible  to be issued prior to the end of this delay time then the pri_op is issued and the timer is reinitialized to tRHD. 3-bit field encodes count  with range 0-7. tRHD = count * 2us." />
            <SpiMxWrErResSusInt value="No Ceiling" value_list="128us,,256us,,512us,,No Ceiling" label="SPI Max write / erase Resume to  Suspend intervals" help_text="This setting specifies the maximum value for the write and erase Resume to Suspend intervals." />
            <SpiSusResEn value="Yes" value_list="Yes,,No" label="SPI Suspend / Resume Enabled" help_text="When this setting is enabled writes and erases may be suspended to allow a read to be issued on the flash device. When this setting is  disabled no transaction will be allowed to the busy flash device." />
            <SoftReBindEnable value="No" value_list="No,,Yes" label="Software Re-Binding Enabled" help_text="When enabled this settings will allow for SPI re-binding to a new PCH during manufacturing and remanufacturing flows prior to platform EOM.  Note: Re-binding to a replacement PCH can only be done a maximum of 5 times before the SPI part needs to be re-flashed." />
        </FlashComponents>
        <HostCpuBiosMasterAccess label="Host CPU / BIOS Master Access">
            <HostCpuWriteAccessIntelRecommended value="0x000A" value_list="0xFFFF,,0x011A,,0x000A,,0x010A,,0x001A,,Custom" label="Host CPU / BIOS Write Access Intel Recommended" help_text="This setting determines write access control for the Host CPU / BIOS. For further details on Region Access Control see the Cannon / Coffee Lake SPI Programming Guide." />
            <HostCpuWriteAccessCustom value="0x0000" label="Host CPU / BIOS Write Access Custom" help_text="This setting determines write access control for the Host CPU / BIOS.  For further details on Region Access Control see the SPI and SMIP Programming Guide" />
            <HostCpuReadAccessIntelRecommended value="0x000F" value_list="0xFFFF,,0x000F,,0x010F,,0x001F,,0x011F,,Custom" label="Host CPU / BIOS Read Access Intel Recommended" help_text="This setting determines read access control for the Host CPU / BIOS. For further details on Region Access Control see the Cannon / Coffee Lake SPI Programming Guide." />
            <HostCpuReadAccessCustom value="0x0000" label="Host CPU / BIOS Read Access Custom" help_text="This setting determines read access control for the Host CPU / BIOS.  For further details on Region Access Control see the SPI and SMIP Programming Guide" />
        </HostCpuBiosMasterAccess>
        <IntelMeMasterAccess label="Intel(R) ME Master Access">
            <MeWriteAccessIntelRecommended value="0x0004" value_list="0xFFFF,,0x0004,,Custom" label="Intel(R) ME Write Access Intel Recommended" help_text="This setting determines write access control for the ME region. For further details on Region Access Control see Cannon / Coffee Lake SPI Programming guide further details." />
            <MeWriteAccessCustom value="0x0000" label="Intel(R) ME Write Access Custom" help_text="This setting determines read access control for the ME region.  For further details on Region Access Control see Canonlake H / LP SPI Programming guide further details." />
            <MeReadAccessIntelRecommended value="0x000D" value_list="0xFFFF,,0x000D,,Custom" label="Intel(R) ME Read Access Intel Recommended" help_text="This setting determines read access control for the ME region. For further details on Region Access Control see Cannon / Coffee Lake SPI Programming guide further details." />
            <MeReadAccessCustom value="0x0000" label="Intel(R) ME Read Access Custom" help_text="This setting determines read access control for the ME region.  For further details on Region Access Control see Canonlake H / LP SPI Programming guide further details." />
        </IntelMeMasterAccess>
        <GbeMasterAccess label="GbE Master Access">
            <GbeWriteAccessIntelRecommended value="0x0008" value_list="0xFFFF,,0x0008,,Custom" label="GbE Write Access Intel Recommended" help_text="This setting determines write access control for the GBE region. For further details on Region Access Control see Cannon / Coffee Lake SPI Programming guide further details." />
            <GbeWriteAccessCustom value="0x0000" label="GbE Write Access Custom" help_text="This setting determines read access control for the GBE region.  For further details on Region Access Control see Canonlake H / LP SPI Programming guide further details." />
            <GbeReadAccessIntelRecommended value="0x0009" value_list="0xFFFF,,0x0009,,Custom" label="GbE Read Access Intel Recommended" help_text="This setting determines read access control for the GBE region. For further details on Region Access Control see Cannon / Coffee Lake SPI Programming guide further details." />
            <GbeReadAccessCustom value="0x0000" label="GbE Read Access Custom" help_text="This setting determines read access control for the GBE region.  For further details on Region Access Control see Canonlake H / LP SPI Programming guide further details." />
        </GbeMasterAccess>
        <EcMasterAccess label="EC Master Access">
            <EcReadAccessIntelRecommended value="0x0101" value_list="0xFFFF,,0x0101,,0x0103,,Custom" label="Embedded Controller Read Access Intel Recommended" help_text="This setting determines read access control for the Embedded Controller region. For further details on Region Access Control see Cannon / Coffee Lake SPI Programming guide further details." />
            <EcReadAccessCustom value="0x0000" label="Embedded Controller Read Access Custom" help_text="This setting determines read access control for the Embedded Controller region.  For further details on Region Access Control see Canonlake H / LP SPI Programming guide further details." />
            <EcWriteAccessIntelRecommended value="0x0100" value_list="0xFFFF,,0x0100,,Custom" label="Embedded Controller Write Access Intel Recommended" help_text="This setting determines write access control for the Embedded Controller region. For further details on Region Access Control see Cannon / Coffee Lake SPI Programming guide further details." />
            <EcWriteAccessCustom value="0x0000" label="Embedded Controller Write Access Custom" help_text="This setting determines write access control for the Embedded Controller region.  For further details on Region Access Control see Canonlake H / LP SPI Programming guide further details." />
        </EcMasterAccess>
        <FlashConfiguration label="Flash Configuration">
            <SpiDualIoReadEnable value="Yes" value_list="No,,Yes" label="Dual I/O Read Enable" help_text="This soft-strap only has effect if Dual I/O Read is discovered as supported via the SFDP." />
            <SpiDualOutReadEnable value="Yes" value_list="No,,Yes" label="Dual Output Read Enable" help_text="This soft-strap only has effect if Dual Output Read is discovered as supported via the SFDP. If parameter table is not detected via the SFDP, this bit has no effect and Dual Output Read is controlled via the Flash Descriptor Component Section Dual Output Fast Read Support bit." />
            <FastReadClockFreq value="48MHz" value_list="17MHz,,30MHz,,48MHz" label="Fast Read Clock Frequency" help_text="This setting allows customers to configure the flash component clock frequency setting for Fast Read. See SPI and SMIP Programming guide further details." />
            <FastReadSupport value="Yes" value_list="No,,Yes" label="Fast Read Supported" help_text="This setting allows customers to enable support for Fast Read capabilities for flash components. See SPI and SMIP Programming guide further details. Note: This setting needs to be enabled when using Dual / Quad enabled components." />
            <InvalidInstruction0 value="0x00000021" label="Invalid Instruction 0" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." />
            <InvalidInstruction1 value="0x00000042" label="Invalid Instruction 1" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." />
            <InvalidInstruction2 value="0x00000060" label="Invalid Instruction 2" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." />
            <InvalidInstruction3 value="0x000000AD" label="Invalid Instruction 3" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." />
            <InvalidInstruction4 value="0x000000B7" label="Invalid Instruction 4" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." />
            <InvalidInstruction5 value="0x000000B9" label="Invalid Instruction 5" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." />
            <InvalidInstruction6 value="0x000000C4" label="Invalid Instruction 6" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." />
            <InvalidInstruction7 value="0x000000C7" label="Invalid Instruction 7" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." />
            <QuadIoReadEnable value="Yes" value_list="No,,Yes" label="Quad I/O Read Enable" help_text="This soft-strap only has effect if Quad I/O Read is discovered as supported via the SFDP." />
            <QuadOutReadEnable value="Yes" value_list="No,,Yes" label="Quad Output Read Enable" help_text="This soft-strap only has effect if Quad Output Read is discovered as supported via the SFDP." />
            <ReadIdAndReadStatClkFreq value="48MHz" value_list="17MHz,,30MHz,,48MHz" label="Read ID and Read Status Clock Frequency" help_text="This setting allows customers to configure the flash component clock frequency setting for Read ID and Read Status. See SPI and SMIP Programming guide further details." />
            <WriteEraseClockFreq value="48MHz" value_list="17MHz,,30MHz,,48MHz" label="Write and Erase Clock Frequency" help_text="This setting allows customers to configure the flash component clock frequency setting for Write and Erase. See SPI and SMIP Programming guide further details." />
        </FlashConfiguration>
        <VsccTable label="Legacy VSCC Table">
            <VsccEntries label="VSCC Entries">
                <VsccEntry label="VSCC Entry">
                    <VsccEntryName value="VsccEntry0" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used.   Note: This is a free form entry field it does not affect actual flash component operation." />
                    <VsccEntryVendorId value="0xEF" label="Vendor ID" help_text="This configures the  JEDEC vendor specific byte ID of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId0 value="0x40" label="Device ID 0" help_text="This configures the  JEDEC device specific byte ID 0 of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId1 value="0x19" label="Device ID 1" help_text="This configures the  JEDEC device specific byte ID 1 of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                </VsccEntry>
                <VsccEntry label="VSCC Entry">
                    <VsccEntryName value="VsccEntry1" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used.   Note: This is a free form entry field it does not affect actual flash component operation." />
                    <VsccEntryVendorId value="0xC8" label="Vendor ID" help_text="This configures the  JEDEC vendor specific byte ID of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId0 value="0x40" label="Device ID 0" help_text="This configures the  JEDEC device specific byte ID 0 of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId1 value="0x19" label="Device ID 1" help_text="This configures the  JEDEC device specific byte ID 1 of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                </VsccEntry>
                <VsccEntry label="VSCC Entry">
                    <VsccEntryName value="VsccEntry2" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used.   Note: This is a free form entry field it does not affect actual flash component operation." />
                    <VsccEntryVendorId value="0xC2" label="Vendor ID" help_text="This configures the  JEDEC vendor specific byte ID of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId0 value="0x20" label="Device ID 0" help_text="This configures the  JEDEC device specific byte ID 0 of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId1 value="0x19" label="Device ID 1" help_text="This configures the  JEDEC device specific byte ID 1 of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                </VsccEntry>
                <VsccEntry label="VSCC Entry">
                    <VsccEntryName value="VsccEntry3" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used.   Note: This is a free form entry field it does not affect actual flash component operation." />
                    <VsccEntryVendorId value="0xEF" label="Vendor ID" help_text="This configures the  JEDEC vendor specific byte ID of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId0 value="0x40" label="Device ID 0" help_text="This configures the  JEDEC device specific byte ID 0 of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId1 value="0x18" label="Device ID 1" help_text="This configures the  JEDEC device specific byte ID 1 of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                </VsccEntry>
                <VsccEntry label="VSCC Entry">
                    <VsccEntryName value="VsccEntry4" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used.   Note: This is a free form entry field it does not affect actual flash component operation." />
                    <VsccEntryVendorId value="0xC8" label="Vendor ID" help_text="This configures the  JEDEC vendor specific byte ID of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId0 value="0x40" label="Device ID 0" help_text="This configures the  JEDEC device specific byte ID 0 of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId1 value="0x18" label="Device ID 1" help_text="This configures the  JEDEC device specific byte ID 1 of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                </VsccEntry>
                <VsccEntry label="VSCC Entry">
                    <VsccEntryName value="VsccEntry5" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used.   Note: This is a free form entry field it does not affect actual flash component operation." />
                    <VsccEntryVendorId value="0xC2" label="Vendor ID" help_text="This configures the  JEDEC vendor specific byte ID of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId0 value="0x20" label="Device ID 0" help_text="This configures the  JEDEC device specific byte ID 0 of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId1 value="0x18" label="Device ID 1" help_text="This configures the  JEDEC device specific byte ID 1 of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                </VsccEntry>
                <VsccEntry label="VSCC Entry">
                    <VsccEntryName value="VsccEntry6" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used.   Note: This is a free form entry field it does not affect actual flash component operation." />
                    <VsccEntryVendorId value="0xEF" label="Vendor ID" help_text="This configures the  JEDEC vendor specific byte ID of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId0 value="0x40" label="Device ID 0" help_text="This configures the  JEDEC device specific byte ID 0 of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId1 value="0x17" label="Device ID 1" help_text="This configures the  JEDEC device specific byte ID 1 of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                </VsccEntry>
                <VsccEntry label="VSCC Entry">
                    <VsccEntryName value="VsccEntry7" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used.   Note: This is a free form entry field it does not affect actual flash component operation." />
                    <VsccEntryVendorId value="0xC8" label="Vendor ID" help_text="This configures the  JEDEC vendor specific byte ID of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId0 value="0x40" label="Device ID 0" help_text="This configures the  JEDEC device specific byte ID 0 of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId1 value="0x17" label="Device ID 1" help_text="This configures the  JEDEC device specific byte ID 1 of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                </VsccEntry>
                <VsccEntry label="VSCC Entry">
                    <VsccEntryName value="VsccEntry8" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used.   Note: This is a free form entry field it does not affect actual flash component operation." />
                    <VsccEntryVendorId value="0x20" label="Vendor ID" help_text="This configures the  JEDEC vendor specific byte ID of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId0 value="0x60" label="Device ID 0" help_text="This configures the  JEDEC device specific byte ID 0 of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId1 value="0x19" label="Device ID 1" help_text="This configures the  JEDEC device specific byte ID 1 of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                </VsccEntry>
                <VsccEntry label="VSCC Entry">
                    <VsccEntryName value="VsccEntry9" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used.   Note: This is a free form entry field it does not affect actual flash component operation." />
                    <VsccEntryVendorId value="0x20" label="Vendor ID" help_text="This configures the  JEDEC vendor specific byte ID of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId0 value="0x70" label="Device ID 0" help_text="This configures the  JEDEC device specific byte ID 0 of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId1 value="0x18" label="Device ID 1" help_text="This configures the  JEDEC device specific byte ID 1 of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                </VsccEntry>
                <VsccEntry label="VSCC Entry">
                    <VsccEntryName value="VsccEntry10" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used.   Note: This is a free form entry field it does not affect actual flash component operation." />
                    <VsccEntryVendorId value="0x20" label="Vendor ID" help_text="This configures the  JEDEC vendor specific byte ID of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId0 value="0x70" label="Device ID 0" help_text="This configures the  JEDEC device specific byte ID 0 of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId1 value="0x17" label="Device ID 1" help_text="This configures the  JEDEC device specific byte ID 1 of the SPI flash  Component see Canonlake H / LP SPI Programming guide for further details." />
                </VsccEntry>
            </VsccEntries>
        </VsccTable>
        <BiosConfiguration label="BIOS Configuration">
            <TopSwapOverride value="1MB" value_list="64KB,,128KB,,256KB,,512KB,,1MB" label="Top Swap Block Size" help_text="This configures the Top Swap Block size for the platform. For further details see Canonlake H / LP Platform Controller Hub EDS." />
            <WriteProtectionEnable value="No" value_list="No,,Yes" label="Write Protection Enable" help_text="Base/limit are inclusive" />
            <ProtectedRangeLimit value="0x0000" label="Protected Range Limit" help_text="This field corresponds to FLA (Flash Linear Address) address bits 26:12 and specifies the upper limit of the protected range. Address bits 11:0 are assumed to be FFFh for the limit comparison. Any address greater than the value programmed in this field is unaffected by this protected range. Note: If either Write or Read protection is enabled, then Limit must be configured greater than or equal to Base.  See SPI and SMIP Programming Guide for more information." />
            <ReadProtectionEnable value="No" value_list="No,,Yes" label="Read Protection Enable" help_text="Base/limit are inclusive" />
            <ProtectedRangeBase value="0x0000" label="Protected Range Base" help_text="This field corresponds to FLA (Flash Linear Address) address bits 26:12 and specifies the lower base of the protected range. Address bits 11:0 are assumed to be 000h for the base comparison. Any address less than the value programmed in this field is unaffected by this protected range. Note: Note: If either Write or Read protection is enabled, then Limit must be configured greater than or equal to Base. See SPI and SMIP Programming Guide for more details." />
        </BiosConfiguration>
        <OEMandPlatformIDs label="OEM and Platform IDs">
            <OemVendorId value="0x0" label="OEM Vendor ID" help_text="This setting allows OEMs to configure their Unique ID into the platform image." />
            <OemPlatformId value="0x0" label="OEM Platform ID" help_text="This setting allows OEMs to configure a Unique Platform ID into the base image." />
        </OEMandPlatformIDs>
        <FPFConfiguration label="FPF Configuration">
            <FpfHwBindingEn value="Enabled" value_list="Disabled,,Enabled" label="FPF Hardware Binding Enabled" help_text="This setting configures the FPF Hardware binding behavior for the platform image.                                                                                                                                                         If this setting is enabled FPF Hardware binding will occur when platform close manufacturing flow is executed with Intel® FPT.                                                                                                                                                        If this setting is disabled FPF Hardware binding will not take place when close manufacturing flow is executed.                                                                                                                                                        Note: For Revenue parts this setting will be ignored and FPF Hardware binding will take place when close manufacturing flow is executed." />
        </FPFConfiguration>
    </FlashSettings>
    <IntelMeKernel label="Intel(R) ME Kernel">
        <Processor>
            <ProcEmulation value="No Emulation" value_list="No Emulation,,EMULATE Intel (R) vPro (TM) capable Processor,,EMULATE Intel (R) Core (TM) branded Processor,,EMULATE Intel (R) Celeron (R) branded Processor,,EMULATE Intel (R) Pentium (R) branded Processor,,EMULATE Intel (R) Xeon E (R) branded Processor,,EMULATE Intel (R) Xeon W (R) Manageability capable Processor" label="Processor Emulation" />
        </Processor>
        <IntelMeFirmwareUpdate label="Intel(R) ME Firmware Update">
            <FwUpdateOemId value="68853622-EED3-4E83-8A86-6CDE315F6B78" label="Firmware Update OEM ID" help_text="This setting allows configuration of an OEM unique ID to ensure that customers can only update their platform with images from the OEM of the platform." />
            <HideMEBxFwUpdCtrl value="Yes" value_list="No,,Yes" label="Hide MEBx Firmware Update Control" help_text="This setting allows customers to hide the Firmware Update option in the MEBx interface." />
            <HmrfpoEnable value="Yes" value_list="No,,Yes" label="Intel(R) ME Region Flash Protection Override" help_text="This setting enables descriptor unlock of the ME Region when the HMRFPO message is sent to firmware prior to BIOS End of POST." />
        </IntelMeFirmwareUpdate>
        <ImageIdentification label="Image Identification">
            <OemTag value="0x00000000" label="OEM Tag" />
        </ImageIdentification>
        <FirmwareDiagnostics label="Firmware Diagnostics">
            <FwAutoBist value="Enabled" value_list="Disabled,,Enabled" label="Automatic Built in Self Test" help_text="This setting enables the firmware Automatic Built in Self Test which is executed during first platform boot after initial image flashing." />
        </FirmwareDiagnostics>
        <PostManufacturingLock label="Post Manufacturing Lock">
            <NvarPostManUnLckd value="No" value_list="Yes,,No" label="Post Manufacturing NVAR Configuration Enabled" help_text="This setting determines if modifications to Customer configuable NVARs is to be allowed after close of manufacturing." />
        </PostManufacturingLock>
        <MctpConfiguration label="MCTP Configuration">
            <MctpStackConfig value="0x920030" label="MCTP Stack Configuration" help_text="Defines the ME's 8-bits MCTP Endpoint IDs for each SMBus physical interface (SMBus, SMLink0 and SMLink1). These values are needed for FW to communicate with MCTP end points. For each of these 3 bytes, a value of 0x00 means not used, and values 0xFF or 0x01 - 0x07 or 0x20 - 0x2F are not allowed." />
            <MctpDevicePortEc value="0x02" />
            <MctpDevicePortSio value="0x00" />
            <MctpDevicePortIsh value="0x00" />
            <MctpDevicePortBmc value="0x00" />
        </MctpConfiguration>
        <IntelMeBootConfiguration label="Intel(R) ME Boot Configuration">
            <PrtcBackupPower value="Exists" value_list="None,,Exists" label="Persistent PRTC Backup Power" help_text="FPF that indicates if the device is designed such that it may lose PRTC power more than 10 times throughout the normal lifecycle of the product and hence has no persistent time or AR protection. At EOM, this value is burned to an FPF, and can never be changed." />
        </IntelMeBootConfiguration>
        <IntelMeMeasuredBootConfiguration label="Intel (R) Me Measured Boot Configuration">
            <MeMeasuredBootState value="Disabled" value_list="Disabled,,Enabled" label="Intel(R) ME Measured Boot State" help_text="When measured boot is enabled firmware will use additional extended registers for all IUPs and Key Manifests that firmware loads and verifies from flash.  Note: When measured boot is enabled any IUPs or firmware updates will require a global reset" />
        </IntelMeMeasuredBootConfiguration>
        <Reserved>
            <Reserved value="No" value_list="No,,Yes" />
        </Reserved>
    </IntelMeKernel>
    <IntelAmt label="Intel(R) AMT">
        <IntelAmtConfiguration label="Intel(R) AMT Configuration">
            <AmtSupported value="Yes" value_list="No,,Yes" label="Intel(R) AMT Supported" help_text="This setting allows customers to disable Intel(R) AMT on the platform and force the platform into Standard Manageability mode.  Note: This setting is only applies to Desktop and Workstation platforms." />
            <NetServicesSupported value="Yes" value_list="Yes,,No" label="Intel(R) ME Network Services Supported" help_text="This setting allows customers to enable / disable Intel(R) ME Network Services on the platform.  Note: If this setting is disabled Intel(R) AMT will also be disabled." />
            <MngAppSupported value="Yes" value_list="No,,Yes" label="Manageability Application Supported" help_text="This setting allows customers to permenantly disable Intel(R) AMT and Standard Manageability mode on the platform." />
            <MngAppPowerUpState value="Enabled" value_list="Disabled,,Enabled" label="Manageability Application initial power-up state" help_text="This setting allows customers to determine the power up state for Intel(R) AMT or Standard Manageability.  Note: If this setting is disabled Intel(R) AMT or Standard Manageability can still be re-enabled through the MEBx interface." />
            <AmtIdleTimeout value="0x0001" label="Intel(R) AMT Idle Timeout" help_text="This setting configures the idle timeout value before Intel(R) AMT enters into an off state." />
            <AmtWdAutoReset value="No" value_list="No,,Yes" label="Intel(R) AMT Watchdog Automatic Reset Enabled" help_text="This setting allows customers to enable the Intel (R) ME firmware to trigger an automatic platform reset if either the MEI or Agent Presence are in a hung state.  Note: This feature only allows one reset at a time when the watchdog expires.  After this feature has triggered a reset it must be re-armed for re-use via management console." />
        </IntelAmtConfiguration>
        <KvmConfiguration label="KVM Configuration">
            <KvmScreenBlnkEnable value="No" value_list="No,,Yes" label="Firmware KVM Screen Blanking" help_text="This setting enables KVM Screen blanking capabilities in the firmware image.  Note: This feature is dependent on processor level support." />
            <KvmSupported value="Yes" value_list="No,,Yes" label="KVM Redirection Supported" help_text="This setting allows customers to enable / disable the KVM Redirection capabilities of the firmware.  Note: If this setting have been set to disabled it cannot be re-enabled once the descriptor has been locked." />
        </KvmConfiguration>
        <ProvisioningConfiguration label="Provisioning Configuration">
            <EhbcEnable value="No" value_list="No,,Yes" label="Embedded Host Based Configuration Enabled" help_text="This setting allows customers to enable / disable Embedded Host Based Configuration. EHBC is primarily intended for use in embedded systems, please leave this setting disabled for business client systems." />
            <PkiDomainSuffix value="" label="PKI Domain Name Suffix" help_text="This setting allows OEMs to pre-configure the Domain Name Suffix used for PKI provisioning in their firmware image.  Note: For normal out-of- box provisioning functionality this setting should be left empty." />
            <OemCustomCert1 label="OEM Customizable Certificate 1">
                <CertActive value="No" value_list="No,,Yes" label="Certificate Enabled" help_text="This setting allows customers to enable PKI provisioning Custom Certificate 1." />
                <CertFriendly value="" label="Certificate Friendly Name" help_text="This setting allows customers to assign a user friendly name for PKI provisioning Custom Certificate 1.  Maximum of 32 characters." />
                <CertStream value="" label="Certificate Stream" help_text="This setting allows customers to input hash stream for PKI provisioning Custom Certificate 1.  If enabled the certificate will be used in addition those already preloaded in base firmware during provisioning.  Note: If the platform is un-configured the Custom Certificate Hash will be deleted." />
            </OemCustomCert1>
            <OemCustomCert2 label="OEM Customizable Certificate 2">
                <CertActive value="No" value_list="No,,Yes" label="Certificate Enabled" help_text="This setting allows customers to enable PKI provisioning Custom Certificate 2." />
                <CertFriendly value="" label="Certificate Friendly Name" help_text="This setting allows customers to assign a user friendly name for PKI provisioning Custom Certificate 2.  Maximum of 32 characters." />
                <CertStream value="" label="Certificate Stream" help_text="This setting allows customers to input hash stream for PKI provisioning custom certificate 2.  If enabled the certificate will be used in addition those already preloaded in base firmware during provisioning.  Note: If the platform is un-configured the Custom Certificate Hash will be deleted." />
            </OemCustomCert2>
            <OemCustomCert3 label="OEM Customizable Certificate 3">
                <CertActive value="No" value_list="No,,Yes" label="Certificate Enabled" help_text="This setting allows customers to enable PKI provisioning Custom Certificate 3." />
                <CertFriendly value="" label="Certificate Friendly Name" help_text="This setting allows customers to assign a user friendly name for PKI provisioning Custom Certificate 3.  Maximum of 32 characters." />
                <CertStream value="" label="Certificate Stream" help_text="This setting allows customers to input hash stream for PKI provisioning Custom Certificate 3.  If enabled the certificate will be used in addition those already preloaded in base firmware during provisioning.  Note: If the platform is un-configured the Custom Certificate Hash will be deleted." />
            </OemCustomCert3>
            <OemDefaultCert1 label="OEM Default Certificate 1">
                <CertActive value="No" value_list="No,,Yes" label="Certificate Enabled" help_text="This setting allows customers to enable PKI provisioning Default certificate 1." />
                <CertFriendly value="" label="Certificate Friendly Name" help_text="This setting allows customers to assign a user friendly name for PKI provisioning Default Certificate 1.  Maximum of 32 characters." />
                <CertStream value="" label="Certificate Stream" help_text="This setting allows customers to input hash stream for PKI provisioning custom certificate 1.  Note: Default Certificates if enabled will be used in addition those already preloaded in firmware during provisioning.  Unlike Customizable Certificates the Default Certificates are not deleted when the platform is un-provisioned." />
            </OemDefaultCert1>
            <OemDefaultCert2 label="OEM Default Certificate 2">
                <CertActive value="No" value_list="No,,Yes" label="Certificate Enabled" help_text="This setting allows customers to enable PKI provisioning Default certificate 2." />
                <CertFriendly value="" label="Certificate Friendly Name" help_text="This setting allows customers to assign a user friendly name for PKI provisioning Default Certificate 2.  Maximum of 32 characters." />
                <CertStream value="" label="Certificate Stream" help_text="This setting allows customers to input hash stream for PKI provisioning custom certificate 2.  Note: Default Certificates if enabled will be used in addition those already preloaded in firmware during provisioning.  Unlike Customizable Certificates the Default Certificates are not deleted when the platform is un-provisioned." />
            </OemDefaultCert2>
            <OemDefaultCert3 label="OEM Default Certificate 3">
                <CertActive value="No" value_list="No,,Yes" label="Certificate Enabled" help_text="This setting allows customers to enable PKI provisioning Default certificate 3." />
                <CertFriendly value="" label="Certificate Friendly Name" help_text="This setting allows customers to assign a user friendly name for PKI provisioning Default Certificate 3.  Maximum of 32 characters." />
                <CertStream value="" label="Certificate Stream" help_text="This setting allows customers to input hash stream for PKI provisioning custom certificate 3.  Note: Default Certificates if enabled will be used in addition those already preloaded in firmware during provisioning.  Unlike Customizable Certificates the Default Certificates are not deleted when the platform is un-provisioned." />
            </OemDefaultCert3>
            <OemDefaultCert4 label="OEM Default Certificate 4">
                <CertActive value="No" value_list="No,,Yes" label="Certificate Enabled" help_text="This setting allows customers to enable PKI provisioning Default certificate 4." />
                <CertFriendly value="" label="Certificate Friendly Name" help_text="This setting allows customers to assign a user friendly name for PKI provisioning Default Certificate 4.  Maximum of 32 characters." />
                <CertStream value="" label="Certificate Stream" help_text="This setting allows customers to input hash stream for PKI provisioning custom certificate 4.  Note: Default Certificates if enabled will be used in addition those already preloaded in firmware during provisioning.  Unlike Customizable Certificates the Default Certificates are not deleted when the platform is un-provisioned." />
            </OemDefaultCert4>
            <OemDefaultCert5 label="OEM Default Certificate 5">
                <CertActive value="No" value_list="No,,Yes" label="Certificate Enabled" help_text="This setting allows customers to enable PKI provisioning Default certificate 5." />
                <CertFriendly value="" label="Certificate Friendly Name" help_text="This setting allows customers to assign a user friendly name for PKI provisioning Default Certificate 5.  Maximum of 32 characters." />
                <CertStream value="" label="Certificate Stream" help_text="This setting allows customers to input hash stream for PKI provisioning custom certificate 5.  Note: Default Certificates if enabled will be used in addition those already preloaded in firmware during provisioning.  Unlike Customizable Certificates the Default Certificates are not deleted when the platform is un-provisioned." />
            </OemDefaultCert5>
        </ProvisioningConfiguration>
        <RedirectionConfiguration label="Redirection Configuration">
            <RedirectionLanguage value="English" label="Redirection Localized Language" help_text="This setting allows customers to configure which localized language will be used initially by firmware for user consent output information (Examples: may be displayed before SOL / KVM session starts)." />
            <RedirectionPrivSecLevel value="Default" value_list="Default,,Enhanced,,Extreme" label="Redirection Privacy / Security Level" help_text="This setting allows customers to configure the Privacy and Security level for redirection operations.  Default enables all redirection ports (User consent is configurable).  Enhanced enables all redirection ports (User consent is required and cannot be disabled).  Extreme disables all redirection capabilities." />
        </RedirectionConfiguration>
        <TlsConfiguration label="TLS Configuration">
            <TlsSupported value="Yes" value_list="No,,Yes" label="Transport Layer Security Supported" help_text="This setting allows customers to enable / disable firmware Transport Layer Security support.  Note: If this is disabled TLS will be permanently disabled in the firmware image." />
        </TlsConfiguration>
    </IntelAmt>
    <PlatformProtection label="Platform Protection">
        <ContentProtection label="Content Protection">
            <PavpSupported value="Yes" value_list="No,,Yes" label="PAVP Supported" help_text="This setting determines if the Protected Audio Video Path (PAVP) feature will be permanently disabled in the FW image." />
            <Lspcon4kdisp value="None" value_list="None,,PortB,,PortC,,PortD" label="LSPCON Internal Display Port 1 - LSPCON / 4K" help_text="This setting determines which port for LSPCON will be connected to the HDCP 2.2 bridge adapter Display 1." />
            <Hdcp5kedisp1 value="PortA" value_list="None,,PortA,,PortB,,PortC,,PortD,,PortF" label="HDCP Internal Display Port 1 - 5K" help_text="This setting determines which port  is connected  for 5K output on Internal Display 1.   Note: Both Display 1 &amp; 2 need to be configured for proper operation." />
            <Hdcp5kedisp2 value="None" value_list="None,,PortA,,PortB,,PortC,,PortD,,PortF" label="HDCP Internal Display Port 2 - 5K" help_text="This setting determines which port  is connected  for 5K output on Internal Display 2. Note: Both Display 1 &amp; 2 need to be configured for proper operation." />
        </ContentProtection>
        <GraphicsuController label="Graphics uController">
            <GucHash value="00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00" label="GuC Encryption Key" help_text="This option is for entering the raw hash 256 bit string for the Graphics uController." />
        </GraphicsuController>
        <PlatformIntegrity label="Hash Key Configuration for Bootguard / ISH">
            <OemPublicKeyHash value="2C BA 98 AE 80 8C 56 E0 72 1A DD 63 E8 27 B7 30 16 58 59 35 91 92 D3 41 1B 97 98 CC 90 65 53 A4" label="OEM Public Key Hash" help_text="Raw hash string for the SHA-256 hash of the OEM public key corresponding to the private key used to sign the OEM Key hash manifest. When manufacture is completed, this hash value is burned into an FPF, and is permament. This value is used to verify the OEM Key hash, and also DnX images. OEM signing is disabled when this hash is set to all 0s." />
            <OemExtInputFile value="D:\Software Programmer Sept 2025\Bios Software\Flash Image Tool\Flash Image Tool 14.0.60.1790\WIN32\20251214_171950_XM25QH256B\Decomp\OEMP.bin" label="OEM Key Manifest Binary" help_text="Signed manifest file containing hashes of keys used for signing  components of image. This setting is only configurable when OEM signing is enabled (See PlatformIntegrity/OemPublicKeyHash)." />
        </PlatformIntegrity>
        <ExclusionRanges label="Exclusion Ranges">
            <Range1Offset value="0x800" label="Range 1 offset" help_text="Range 1 offset covers manifest, cannot be changed" />
            <Range1Size value="0x400" label="Range 1 size" help_text="Range 1 size covers manifest, cannot be changed" />
            <Range2Offset value="0x80" label="Range 2 offset" help_text="Range 2 offset covers OEM defined unprotected range start" />
            <Range2Size value="0x20" label="Range 2 size" help_text="Range 2 size covers OEM defined unprotected range length" />
            <Range3Offset value="0x0" label="Range 3 offset" help_text="Range 3 offset covers OEM defined unprotected range start" />
            <Range3Size value="0x0" label="Range 3 size" help_text="Range 3 size covers OEM defined unprotected range length" />
            <Range4Offset value="0x0" label="Range 4 offset" help_text="Range 4 offset covers OEM defined unprotected range start" />
            <Range4Size value="0x0" label="Range 4 size" help_text="Range 4 size covers OEM defined unprotected range length" />
            <Range5Offset value="0x0" label="Range 5 offset" help_text="Range 5 offset covers OEM defined unprotected range start" />
            <Range5Size value="0x0" label="Range 5 size" help_text="Range 5 size covers OEM defined unprotected range length" />
            <Range6Offset value="0x0" label="Range 6 offset" help_text="Range 6 offset covers OEM defined unprotected range start" />
            <Range6Size value="0x0" label="Range 6 size" help_text="Range 6 size covers OEM defined unprotected range length" />
            <Range7Offset value="0x0" label="Range 7 offset" help_text="Range 7 offset covers OEM defined unprotected range start" />
            <Range7Size value="0x0" label="Range 7 size" help_text="Range 7 size covers OEM defined unprotected range length" />
            <Range8Offset value="0x0" label="Range 8 offset" help_text="Range 8 offset covers OEM defined unprotected range start" />
            <Range8Size value="0x0" label="Range 8 size" help_text="Range 8 size covers OEM defined unprotected range length" />
        </ExclusionRanges>
        <DescConfiguration label="Descriptor Configuration">
            <FdvEnabled value="No" value_list="No,,Yes" label="Flash Descriptor Verification Enabled" />
            <DescSigningKey value="" label="Descriptor Signing Key" help_text="This is the path to the private key used to sign the Descriptor, while public key hash of it is included in the OEM hash manifest.  This setting is only configurable when Flash Descriptor Verification is enabled (See PlatformIntegrity/FdvEnabled)." />
            <excludeMasterAccsess value="Yes" value_list="No,,Yes" label="exclude master access in the signature" help_text="include/exclude master access in the signature." />
        </DescConfiguration>
        <BootGuardConfiguration label="Boot Guard Configuration">
            <BtGuardKeyManifestId value="0xF" label="Key Manifest ID" help_text="ODM identifier used during the Key manifest authentication process. This setting is only configurable, and must be non-0, when OEM Public Key Hash is set (See PlatformIntegrity/OemPublicKeyHash)." />
            <BtGuardProfileConfig value="Boot Guard Profile 5 - FVME" value_list="Boot Guard Profile 0 - No_FVME,,Boot Guard Profile 3 - VM,,Boot Guard Profile 4 - FVE,,Boot Guard Profile 5 - FVME" label="Boot Guard Profile Configuration " help_text="Boot Guard Profile 0 - Legacy is for platforms that do not wish to enable Boot Guard boot block verification or measurement protection.  When manufacture is completed, this  value is burned into an FPF, and is permanent. This setting is only configurable when OEM signing is enabled (See PlatformIntegrity/OemPublicKeyHash)." />
            <BtGuardCpuDebugEnable value="Enabled" value_list="Enabled,,Disabled" label="CPU Debugging" help_text="This setting determines if CPU debug modes will be displayed.  When set to 'Yes' CPU debugging is enabled." />
            <BtGuardBspInitEnable value="Enabled" value_list="Enabled,,Disabled" label="BSP Initialization" help_text="This setting determines BSP behavior when it receives an INIT signal.  When set to 'Yes', when BSP receives an INIT, BSP will signal an error to the BSS register and enter unrecoverable shutdown." />
            <BtGuardS3Optimize value="Enabled" value_list="Enabled,,Disabled" label="S3 Optimization" help_text="S3 Optimization capability has been deprecated from Intel(R) CSME FW. Refrain from updating or using this field." />
        </BootGuardConfiguration>
        <IntelPttConfiguration label="Intel(R) PTT Configuration">
            <PttSupported value="Yes" value_list="No,,Yes" label="Intel(R) PTT Supported" help_text="This setting permanently disables Intel(R) PTT in the firmware image." />
            <PttPwrUpState value="Disabled" value_list="Disabled,,Enabled" label="Intel(R) PTT initial power-up state" />
            <PttSupportedFpf value="Yes" value_list="No,,Yes" label="Intel(R) PTT Supported [FPF]" help_text="This setting will permanently disable Intel(R) PTT through platform FPFs.  Caution: Using this option will permanently disable Intel(R) PTT on the platform hardware." />
            <PttRpmcSupported value="No" value_list="No,,Yes" label="Intel(R) PTT RPMC Supported" help_text="This setting determines if RPMC is enabled for Intel(R) PTT. Note: The SPI parts being used need to support RPMC In order to use this feature." />
            <PttRpmcRebindEn value="No" value_list="No,,Yes" label="Intel(R) PTT RPMC Rebinding Enabled" help_text="This setting determines if Rebinding of RPMC enabled SPI parts is enabled." />
        </IntelPttConfiguration>
        <TpmOverSpiBusConfiguration label="TPM Over SPI Bus Configuration">
            <SpiOverTpmClkFreq value="30MHz" value_list="17MHz,,30MHz,,48MHz" label="TPM Clock Frequency" help_text="This setting determines the clock frequency setting to be used for the TPM over SPI bus." />
            <SpiOverTpmBusEnable value="Yes" value_list="No,,Yes" label="TPM Over SPI Bus Enabled" help_text="This setting determines the clock frequency setting to be used for the TPM over SPI bus." />
        </TpmOverSpiBusConfiguration>
        <BiosGuardConfiguration label="BIOS Guard Configuration">
            <BiosGrdProtOvrdEn value="Yes" value_list="No,,Yes" label="BIOS Guard Protection Override Enabled" help_text="This setting allows BIOS Guard to bypass SPI flash controller protections (i.e. Protected Range Registers and Top Swap)." />
        </BiosGuardConfiguration>
        <TxtConfiguration label="TXT Configuration">
            <TxtSupported value="No" value_list="No,,Yes" label="TXT Supported" help_text="This setting determines is enabled for the platform." />
        </TxtConfiguration>
        <CryptoHardwareSupport label="Crypto Hardware Support">
            <CryptoHwSupport value="Yes" value_list="Yes,,No" label="Crypto HW Support" help_text="This setting can be used to disable crypto funtionality. This settings disables all crypto dependent features." />
        </CryptoHardwareSupport>
        <TrustedDeviceSetup label="Platform Trusted Device Setup Support">
            <EnableTDS value="No" value_list="No,,Yes" label="Enable TDS Capabilities" help_text="This setting enables Intel(R) Trusted Device Setup on the platform" />
        </TrustedDeviceSetup>
    </PlatformProtection>
    <Icc label="Integrated Clock Controller">
        <IccPolicies label="Integrated Clock Controller Policies">
            <BootProfile value="Profile 0" value_list="Profile 0" label="Boot Profile" help_text="Profile applied during each boot." />
            <FailsafeBootProfile value="Profile 0" value_list="Profile 0" label="Failsafe Boot Profile" help_text="Boot profile used when system instability is detected." />
            <ProfileChangeable value="true" value_list="true,,false" label="Profile Changeable" help_text="True = Allows user to change boot profile via BIOS menu or 3rd party application False = Prevents user from changing boot profile via BIOS or 3rd party application.  Note: When false, Failsafe Boot Profile must be the same as Boot Profile." />
            <BclkClockConfiguration label="BCLK Clock Build-time Configurations">
                <IsBclkConfValid value="Disabled" value_list="Disabled,,Enabled" label="BCLK Build-time Clock Configuration Enabled" help_text="Enables/disables BCLK Build-time Clock configuration values for adaptive profiles." />
                <BclkFreq value="100.000" label="BCLK Clock Frequency" help_text="Displays the nominal frequency for the selected clock." />
                <BclkSsc value="0.45" label="BCLK Spread setting" help_text="Displays the percentage of  Spread setting for the selected clock." />
            </BclkClockConfiguration>
            <Profiles>
                <Profile>
                    <ProfileName value="Profile 0" label="Profile Name" help_text="Editable text string stored with the profile for easy identification." />
                    <ProfileType value="Standard" value_list="Standard,,Adaptive" label="Profile Type" help_text="Specifies the profile template used when creating the profile.  Intel (R) ME image has to be loaded to enable other ICC profile settings." />
                    <ClockRangeDefinitionRecord label="Clock Range Definition Record">
                        <BClkSscHalt value="No" value_list="No,,Yes" label="BCLK SSC Halt Allowed" help_text="If set to Yes, the spread generator can be enabled and disabled at runtime." />
                    </ClockRangeDefinitionRecord>
                    <ClockOutputConfiguration label="Clock Output Configuration">
                        <ClkoutITPXDP value="Enabled" value_list="Disabled,,Enabled" label="ITPXDP" help_text="Enable/Disable the CLKOUT_ITPXDP differential output buffer." />
                        <ClkoutSRC0 value="Enabled" value_list="Disabled,,Enabled" label="SRC0" help_text="Enable/Disable the CLKOUT_SRC0 differential output buffer." />
                        <ClkoutSRC1 value="Enabled" value_list="Disabled,,Enabled" label="SRC1" help_text="Enable/Disable the CLKOUT_SRC1 differential output buffer." />
                        <ClkoutSRC2 value="Enabled" value_list="Disabled,,Enabled" label="SRC2" help_text="Enable/Disable the CLKOUT_SRC2 differential output buffer." />
                        <ClkoutSRC3 value="Enabled" value_list="Disabled,,Enabled" label="SRC3" help_text="Enable/Disable the CLKOUT_SRC3 differential output buffer." />
                        <ClkoutSRC4 value="Enabled" value_list="Disabled,,Enabled" label="SRC4" help_text="Enable/Disable the CLKOUT_SRC4 differential output buffer." />
                        <ClkoutSRC5 value="Enabled" value_list="Disabled,,Enabled" label="SRC5" help_text="Enable/Disable the CLKOUT_SRC5 differential output buffer." />
                        <ClkoutCpunsscPnPath value="Direct XTAL IN / Out Path" value_list="HDA PLL Path,,Direct XTAL IN / Out Path" label="CLKOUT CPUNSSC P/N Clock Path Generation" help_text="This setting determines if CLKOUT_CPUNSSC_P/N Clock Path is generated through the HDA_PLL or from Direct XTAL IN/OUT." />
                    </ClockOutputConfiguration>
                    <PwrManagementConfiguration label="Power Management Configuration">
                        <ClkreqMapSRC0 value="GPP_B5" value_list="GPP_B5,,GPP_B6,,GPP_B7,,GPP_B8,,GPP_B9,,GPP_B10" label="SRC0 CLKREQ# Mapping" help_text="Assign the CLKREQ# signal associated with CLKOUT_SRC0. Please note that remapping of any SRC CLKREQ# would require swapping the relevant status of SRC# under Clock Output Configuration to match the remapping." />
                        <ClkreqMapSRC1 value="GPP_B6" value_list="GPP_B5,,GPP_B6,,GPP_B7,,GPP_B8,,GPP_B9,,GPP_B10" label="SRC1 CLKREQ# Mapping" help_text="Assign the CLKREQ# signal associated with CLKOUT_SRC1. Please note that remapping of any SRC CLKREQ# would require swapping the relevant status of SRC# under Clock Output Configuration to match the remapping." />
                        <ClkreqMapSRC2 value="GPP_B7" value_list="GPP_B5,,GPP_B6,,GPP_B7,,GPP_B8,,GPP_B9,,GPP_B10" label="SRC2 CLKREQ# Mapping" help_text="Assign the CLKREQ# signal associated with CLKOUT_SRC2. Please note that remapping of any SRC CLKREQ# would require swapping the relevant status of SRC# under Clock Output Configuration to match the remapping." />
                        <ClkreqMapSRC3 value="GPP_B8" value_list="GPP_B5,,GPP_B6,,GPP_B7,,GPP_B8,,GPP_B9,,GPP_B10" label="SRC3 CLKREQ# Mapping" help_text="Assign the CLKREQ# signal associated with CLKOUT_SRC3. Please note that remapping of any SRC CLKREQ# would require swapping the relevant status of SRC# under Clock Output Configuration to match the remapping." />
                        <ClkreqMapSRC4 value="GPP_B9" value_list="GPP_B5,,GPP_B6,,GPP_B7,,GPP_B8,,GPP_B9,,GPP_B10" label="SRC4 CLKREQ# Mapping" help_text="Assign the CLKREQ# signal associated with CLKOUT_SRC4. Please note that remapping of any SRC CLKREQ# would require swapping the relevant status of SRC# under Clock Output Configuration to match the remapping." />
                        <ClkreqMapSRC5 value="GPP_B10" value_list="GPP_B5,,GPP_B6,,GPP_B7,,GPP_B8,,GPP_B9,,GPP_B10" label="SRC5 CLKREQ# Mapping" help_text="Assign the CLKREQ# signal associated with CLKOUT_SRC5. Please note that remapping of any SRC CLKREQ# would require swapping the relevant status of SRC# under Clock Output Configuration to match the remapping." />
                    </PwrManagementConfiguration>
                </Profile>
            </Profiles>
        </IccPolicies>
    </Icc>
    <NetworkingConnectivity label="Networking &amp; Connectivity">
        <NetworkingConfiguration label="Networking Configuration">
            <PlatformVproNIC label="Platform vPro 2.5G Wired LAN (i.e. I225)">
                <vproNicEnabled value="No" value_list="No,,Yes" label="Platform vPro 2.5G Wired LAN Enabled" help_text="YES = Discrete NIC enabled in platform NO = Integrated GBE LAN enabled in platform" />
                <vproNicSMBusAddress value="0x0" label="Platform vPro 2.5G Wired LAN SMBUS slave address" help_text="Platform discrete NIC slave address Note: Input needs to be in HEX format(OEM specific), e.g. 0x12" />
            </PlatformVproNIC>
            <DockingStation label="Intel vPro (TM) for Thunderbolt (TM) 3/ USB-C Dock station">
                <vproDockEnabled value="No" value_list="No,,Yes" label="vPro Dock Enabled" help_text="YES = Enables communication with, vPro supporting NIC, via TBT dock NO = No support for vPro dock solution" />
                <TypeCPortRetimerMCTPSmbusAddr value="0x0" label="vPro 2.5G Wired LAN on dock slave SMBUS Address" help_text="vPro 2.5G Wired LAN slave address Note: Input needs to be in HEX format(OEM specific), e.g. 0x12" />
                <TypeCPort1RetimerI2cAddress value="0x20" label="Type-C Port1 Re-Timer I2C Address" help_text="This setting configures the Intel(R) SMBus I2C Address. Note: Input needs to be in HEX format(OEM specific), e.g. 0x12" />
                <TypeCPort2RetimerI2cAddress value="0x21" label="Type-C Port2 Re-Timer I2C Address" help_text="This setting configures the Intel(R) SMBus I2C Address. Note: Input needs to be in HEX format(OEM specific), e.g. 0x12" />
                <TypeCPort3RetimerI2cAddress value="0x22" label="Type-C Port3 Re-Timer I2C Address" help_text="This setting configures the Intel(R) SMBus I2C Address. Note: Input needs to be in HEX format(OEM specific), e.g. 0x12" />
                <TypeCPort4RetimerI2cAddress value="0x23" label="Type-C Port4 Re-Timer I2C Address" help_text="This setting configures the Intel(R) SMBus I2C Address. Note: Input needs to be in HEX format(OEM specific), e.g. 0x12" />
            </DockingStation>
        </NetworkingConfiguration>
        <WiredLanConfiguration label="Wired LAN Configuration">
            <MELanPowerWell value="SLP_LAN#" value_list="Core Well,,SUS Well,,ME Well,,SLP_LAN#" label="LAN Power Well" help_text="This setting allows the customer to configure the powerwell that will be used by Intel(R) Integrated LAN.  Note: Recommended setting is SLP_LAN#." />
            <LanPhyPwrUpTime value="100ms" value_list="100ms,,50ms" label="LAN PHY Power Up Time" help_text="This bit determines how long the delay for LAN PHY to power up after de-assertion of  SLP_LAN#" />
            <LanEnable value="Yes" value_list="Yes,,No" label="Intel(R) Integrated Wired LAN Enabled" help_text="This setting allows customers to enable / disable Intel(R) Integrated LAN operation over the PCIe Port selected by the GbE PCIe Port Select option." />
            <GbePCIePortSelect value="Port9" value_list="Port7,,Port8,,Port9,,Port13,,Port14" label="GbE PCIe Port Select" help_text="This setting allows customers to configure the PCIe Port that will Intel(R) Integrated LAN will operate on." />
            <GbePHYSmbAddrs value="0x00000064" label="GbE PHY SMBus Address" help_text="This is the Intel PHY SMBus address.  This field must be programmed to 64h.  GbE PHY SMBus Address and GbE MAC address have to be programmed to 64h and 70h in  order to ensure proper arbitration of SMBus communication between the Intel integrated MAC and PHY." />
            <GbeMacSmbAddrsEn value="Yes" value_list="No,,Yes" label="GbE MAC SMBus Address Enabled" help_text="This enables the Intel(R) Integrated Wired LAN MAC SMBus address. Note: This setting must be enabled if using Intel(R) Integrated LAN." />
            <GbeMacSmbAddrs value="0x00000070" label="GbE MAC SMBus Address" help_text="This setting configures Intel(R) Integrated Wired LAN MAC SMBus address to accept SMBus cycles from the PHY. Note: Recommended setting is 70h." />
            <GbePhyPcieEnable value="Yes" value_list="No,,Yes" label="Intel(R) PHY over PCIe Enabled" help_text="This setting allows customers to enable / disable Intel(R) Integrated LAN operation over the PCIe Port selected by the GbE PCIe Port Select option." />
            <PhyConnected value="PHY on SMLink0" value_list="No PHY Connected,,PHY on SMBus,,PHY on SMLink0,,PHY on SMLink1" label="PHY Connection" help_text="This selects which SMBus network is used to connect GbE PHY to MAC/PCH.  Note: This setting will be greyed out if GbE regions is disabled." />
            <LanPhyPwrCtrlGpd11Config value="Enable as LANPHYPC" value_list="Enable as GPD11,,Enable as LANPHYPC" label="LAN PHY Power Control GPD11 Signal Configuration" help_text="This setting allows the user to assign the LAN PHY Power Control signal to GbE or as GDP11. Note: If using Intel(R) Integrated LAN this setting should be set to &quot;&quot;Enable as LANPHYPC&quot;&quot;." />
        </WiredLanConfiguration>
        <WirelessLanConfiguration label="Wireless LAN Configuration">
            <MeClinkEnable value="Yes" value_list="No,,Yes" label="Intel(R) ME CLINK Signal Enabled" help_text="This setting allows customers to enable / disable the Wireless LAN CLINK signal through Intel(R) ME firmware.  Note: For using Intel(R) vPro Wireless solutions this should be set to Yes." />
            <SlpWlanGdp9Config value="Enable as SLP_WLAN#" value_list="Enable as SLP_WLAN#,,Enable as GPD9" label="SLP_WLAN# / GDP9 Signal Configuration" help_text="This setting allows user the to assign the WLAN Power Control signal to WLAN or as GDP9. Note: If using Intel(R) Wireless LAN this setting should be set to &quot;&quot;Enable as SLP_WLAN#&quot;&quot;." />
            <WlanUcode value="0x2F0 QUASAR" label="WLAN Microcode" help_text="This setting allows OEMs to configure which Intel(R) Wireless LAN card microcode to load into the firmware image." />
            <MEWlanPowerWell value="SLP_WLAN#" value_list="Disabled,,Core Well || SLP_S3#,,Primary Well || SLP_SUS#,,ME Well || SLP_A#,,SLP_WLAN#" label="WLAN Power Well" />
        </WirelessLanConfiguration>
    </NetworkingConnectivity>
    <InternalPchBuses label="Internal PCH Buses">
        <PchTimerConfiguration label="PCH Timer Configuration">
            <t573TimingConfig value="1ms" value_list="100ms,,50ms,,5ms,,1ms" label="PCH clock output stable to PROCPWRGD high (tPCH45)" help_text="This setting configures the minimum timing from XCK_PLL locked to CPUPWRGD high. For further details see Canonlake LP Platform Controller Hub EDS." />
            <t36TimerEnable value="Disabled" value_list="Disabled,,Enabled" label="PCIe Power Stable Timer (tPCH33)" help_text="This setting configures the enables / disables the tPCH33 timer. When enabled PCH will count 99ms from PWROK assertion before PLTRST# is de-asserted. Note: The recommended setting is &quot;&quot;Disabled&quot;&quot;" />
            <t1001TimingConfig value="1ms" value_list="1ms,,5ms,,2ms" label="PROCPWRGD and SYS_PWROK high to SUS_STAT# de-assertion (tPCH46)" help_text="This setting configures the minimum timing from CPUPWRGD assertion to SUS_STAT#. For further details see Canonlake LP Controller Hub EDS." />
            <ApwrokTiming value="2ms" value_list="2ms,,4ms,,8ms,,15ms" label="APWROK Timing" help_text="This soft strap determines the timing between the SLP_A# pin de-asserting and the APWROK timer expiration." />
        </PchTimerConfiguration>
        <SmbusSmlinkConfiguration label="SMBus / SMLink Configuration">
            <SMBusAsdAddress value="0x00000000" label="Intel(R) SMBus ASD Address" help_text="This setting configures the Intel(R) SMBus Alert Sending Device Address. For details see Canonlake H / LP SPI Programming guide further details." />
            <SMBusAsdEnable value="No" value_list="No,,Yes" label="Intel(R) SMBus ASD Address Enabled" help_text="This setting enables / disables the Intel(R) SMBus Alert Sending Device. For details see Skylake H / LP or Lewisburg SPI Programming guide further details." />
            <SMBusAsfId value="0x00000000" label="Intel(R) SMBus Subsystem Vendor and Device ID for ASF" help_text="This setting configures the Intel(R) SMBus Subsystem Vendor and Device ID for ASF. For details see Canonlake H / LP SPI Programming guide further details." />
            <SMBusI2cAddress value="0x00000000" label="Intel(R) SMBus I2C Address" help_text="This setting configures the Intel(R) SMBus I2C Address. Note: This setting is only used for testing purposes. The recommended setting is &quot;&quot;0000000&quot;&quot;" />
            <SMBusI2cEnable value="No" value_list="No,,Yes" label="Intel(R) SMBus I2C Address Enabled" help_text="This setting enables / disables the Intel(R) SMBus I2C Address. Note: This setting is only used for testing purposes. The recommended setting is &quot;&quot;No&quot;&quot;" />
            <SMBusMctpAddress value="0x00000000" label="Intel(R) SMBus MCTP Address" help_text="This setting configures the Intel(R) SMBus MCTP Address. Note: This setting is only used for testing purposes. The default setting is &quot;&quot;0000000&quot;&quot;" />
            <SMBusMctpEnable value="No" value_list="No,,Yes" label="Intel(R) SMBus MCTP Address Enabled" help_text="This setting enables / disables the Intel(R) SMBus MCTP Address. Note: This setting is only used for testing purposes. The recommended setting is &quot;&quot;No&quot;&quot;" />
            <SMBusTcoSlaveSelect value="Intel(R) SMBus" value_list="Intel(R) SMBus,,SMLink 0" label="SMBus / SMLink TCO Slave Connection" help_text="This setting configures the TCO Slave connection to ether the Intel(R) SMBus or SMLink0. For further details see Canon LP Platform Controller Hub EDS." />
            <SLink0Enable value="Yes" value_list="No,,Yes" label="SMLink0 Enabled" help_text="This setting enables / disables SMLink0 interface. For further details see Canonlake H / LP Platform Controller Hub EDS. Note: If using Intel(R) NFC this setting must be set to &quot;&quot;Yes&quot;&quot;." />
            <SLink0freq value="1 MHz" value_list="100 KHz,,400 KHz,,1 MHz" label="SMLink0 Frequency" help_text="This setting determines the frequency at which the SMLink0 will operate. Note: The recommended setting is &quot;&quot;1MHz&quot;&quot;" />
            <SLink1I2cAddress value="0x00000000" label="SMLink1 I2C Target Address" help_text="This setting configures SMLink1 I2C Target Address. For further details see Canonlake H / LP Platform Controller Hub EDS." />
            <SLink1I2cEnable value="No" value_list="No,,Yes" label="SMLink1 I2C Target Address Enabled" help_text="This setting configures SMLink1 I2C Target Address. For further details see Skylake H / LP or Lewisburg Platform Controller Hub EDS." />
            <SLink1GPTargetAddress value="0x00000000" label="SMLink1 GP Target Address" help_text="This setting configures SMLink1 GP Target Address. For further details see Canonlake LP Platform Controller Hub EDS." />
            <SLink1GPTargetEnable value="No" value_list="No,,Yes" label="SMLink1 GP Target Address Enabled" help_text="This setting enables / disables SMLink1 GP Target Address interface. For further details see Canonlake LP Platform Controller Hub EDS. Note: This setting must be set to &quot;&quot;Yes&quot;&quot; if using PCH / MCP Thermal reporting." />
            <SLink1Enable value="Yes" value_list="No,,Yes" label="SMLink1 Enabled" help_text="This setting enables / disables SMLink1 interface. For further details see Canonlake H / LP or Platform Controller Hub EDS.   Note: This setting must be set to &quot;Yes&quot; if using PCH / MCP Thermal reporting." />
            <SLink1freq value="1 MHz" value_list="100 KHz,,400 KHz,,1 MHz" label="SMLink1 Frequency" help_text="This setting determines the frequency at which the SMLink1 will operate. Note: The recommended setting is &quot;&quot;100KHz&quot;&quot;" />
            <SmbAlrtModeConfig value="Enable as GPP_C2" value_list="Enable as GPP_C2,,Enable as Intel(R) SMBus ASD" label="Intel(R) SMBus ASD Mode Configuration" help_text="This setting determines the native mode of operation for the Intel(R) SMBus ASD signal." />
            <SLink0MctpAddress value="0x00000000" label="Intel(R) SMLink0 MCTP Address" help_text="This setting configures the Intel(R) SMLink0 MCTP Address.   Note: This setting is only used for testing." />
            <SLink0MctpEnable value="No" value_list="No,,Yes" label="Intel(R) SMLink0 MCTP Address Enabled" help_text="This setting enables / disables the Intel(R) SMLink0 MCTP Address.   Note: This setting is only used for testing purposes." />
            <SLink0I2cAddress value="0x00000000" label="SMLink0 I2C Address" help_text="This setting configures the SMLink0 I2C Address.   Note: This setting is used as a part of the Intel(R) vPro Thunderbolt(tm) dock configuration." />
            <SMLink0I2cEnable value="No" value_list="No,,Yes" label="SMLink0 I2C Address Enabled" help_text="This setting enables / disables the SMLink0 I2C Address.   Note: This setting is used as a part of the Intel(R) vPro Thunderbolt(tm) dock configuration." />
        </SmbusSmlinkConfiguration>
        <DmiConfiguration label="DMI Configuration">
            <DmiLaneReversal value="No" value_list="No,,Yes" label="DMI Lane Reversal" help_text="This setting allow the DMI Lane signals to be reversed. For further details see Canonlake H / LP Platform Controller Hub EDS." />
            <DmiPciPortStagger value="Yes" value_list="No,,Yes" label="DMI Port Staggering Enabled" help_text="This setting configures DMI for Port Staggering. For further details see Canonlake LP Platform Controller Hub EDS." />
        </DmiConfiguration>
        <OpiDmiConfiguration label="OPI Configuration">
            <OpiLinkSpeed value="4GT/s" value_list="2GT/s,,4GT/s" label="OPI / DMI Link Speed" help_text="This setting configures the OPI Link Speed. For further details see Canonlake PCH EDS." />
            <OpiLinkVoltage value="0.95 Volts" value_list="0.85 Volts,,0.95 Volts,,1.05 Volts" label="OPI /DMI Link Voltage" help_text="This setting configures the OPI Link Voltage. For further details see Canonlake PCH EDS." />
            <OpiLinkWidth value="8 Lanes" value_list="1 Lane,,2 Lanes,,4 Lanes,,8 Lanes" label="OPI / DMI Link Width" help_text="This setting configures the OPI Link Width. For further details see Canonlake PCH EDS." />
        </OpiDmiConfiguration>
        <EspiConfiguration label="eSPI Configuration">
            <EspiEcBusfreq value="48MHz" value_list="20MHz,,24MHz,,30MHz,,48MHz,,60MHz" label="eSPI / EC Bus Frequency" help_text="This setting determines the maximum frequency of the eSPI bus that is supported by the eSPI Master and platform configuration.          Note: The actual frequency depends on trace length, number of eSPI Slaves, etc." />
            <EspiEcMaxIoMode value="Single, Dual and Quad" value_list="Single,,Single and Dual,,Single and Quad,,Single, Dual and Quad" label="eSPI / EC Maximum I/O Mode" help_text="This setting determines the maximum IO Mode (Single/Dual/Quad) of the eSPI bus that is supported by the eSPI Master and specific platform configuration.           Note: The actual IO Mode of the eSPI bus will be the minimum of this field and the Slave's maximum IO Mode advertised in its General Capabilities register." />
            <EspiEcCrcCheckEnable value="Yes" value_list="Yes,,No" label="eSPI / EC CRC Check Enabled" help_text="This setting enables CRC checking on eSPI Slave 0 channel." />
            <EspiEcMaxOutReqMstrFlCh value="2" value_list="2,,1" label="eSPI / EC Max Outstanding Request for  Master Attached Flash Channel" help_text="This setting configures the maximum outstanding requests allowed over the Master Attached Flash channel." />
            <EspiEcSlvAtchdFlshMor value="Single" value_list="Single,,Multiple" label="eSPI / EC Slave Attached Flash Multiple  Outstanding Requests Enable" help_text="This setting configured Slave Attached Flash for Multiple outstanding requests." />
            <EspiEcSlvAtchdFlshOoo value="In Order" value_list="In Order,,Out of Order" label="eSPI / EC Slave Attached Flash Channel OOO  Enable" help_text="This setting configured Slave Attached Flash channel Out of Order capabilities." />
        </EspiConfiguration>
    </InternalPchBuses>
    <Power>
        <PlatformPower label="Platform Power">
            <SlpS5Gdp10Config value="Enable as SLP_S5#" value_list="Enable as SLP_S5#,,Enable as GPD10" label="SLP_S5# / GPD10 Signal Configuration" help_text="This setting allows the user to assign the SLP_S5# Power Control signal as SLP_S5# or as GDP10. For further details see Canonlake H / LP Platform Controller Hub EDS." />
            <SlpS3Gdp4Config value="Enable as SLP_S3#" value_list="Enable as SLP_S3#,,Enable as GPD4" label="SLP_S3# / GPD4 Signal Configuration" help_text="This setting allows the user to assign the SLP_S3# Power Control signal as SLP_S3# or as GDP4. For further details see Comet Lake-LP Platform Controller Hub EDS." />
            <SlpS4Gdp5Config value="Enable as SLP_S4#" value_list="Enable as SLP_S4#,,Enable as GPD5" label="SLP_S4# / GPD5 Signal Configuration" help_text="This setting allows the user to assign the SLP_S4# Power Control signal as SLP_S4# or as GDP5. For further details see Canonlake H / LP Platform Controller Hub EDS." />
            <SlpAGpd6Config value="Enable as SLP_A#" value_list="Enable as SLP_A#,,Enable as GPD6" label="SLP_A# / GPD6 Signal Configuration" help_text="This setting allows the user to assign the SLP_A# Power Control signal as SLP_A# or as GDP6. For further details see Canonlake H / LP Platform Controller Hub EDS." />
            <SlpS0TunnelDis value="Disabled" value_list="Enabled,,Disabled" label="SLP_S0# Tunnel" help_text="This setting Enables / Disables the tunneling of the SLP_S0# pin over ESPI to the EC when in ESPI mode." />
        </PlatformPower>
        <DeepSx label="Deep Sx">
            <DeepSxSupportEnable value="No" value_list="No,,Yes" label="Deep Sx Enabled" help_text="This setting enables / disables support for Deep Sx operation. For further details see Skylake H / LP Platform Controller Hub EDS. Note: Support for Deep Sx is board design dependent." />
        </DeepSx>
        <PchThermalReporting label="PCH Thermal Reporting">
            <PchThrmlRprtngEn value="Yes" value_list="Yes,,No" label="Thermal Power Reporting Enabled" help_text="This setting enabled a once-per-second timer interrupt is enabled which triggers firmware to report power and temperature information as enabled by configuration registers.  Note: When this setting is disabled ensure that the once-per-second timer interrupt associated with this feature is also disabled." />
        </PchThermalReporting>
    </Power>
    <IntegratedSensorHub label="Integrated Sensor Hub">
        <IshSupported value="No" value_list="Yes,,No" label="Integrated Sensor Hub Supported" help_text="This setting allows customers to disable ISH on the platform." />
        <IshPowerUpState value="Disabled" value_list="Disabled,,Enabled" label="Integrated Sensor Hub Initial Power State" help_text="This setting allows customers to determine the power up state for ISH." />
        <IshImage label="ISH Image">
            <Length value="0x40000" label="Integrated Sensor Hub Length" help_text="Total size (in bytes) of the ISH code partition including reserved space. It is recommended to be at least 256kb." />
            <InputFile value="" label="ISH Input File" help_text="Path to your ISH firmware binary file." />
        </IshImage>
        <IshData label="ISH Data">
            <PdtBinary value="D:\Software Programmer Sept 2025\Bios Software\Flash Image Tool\Flash Image Tool 14.0.60.1790\WIN32\20251214_171950_XM25QH256B\Decomp\PdtBinary.bin" label="ISH PDT Binary File" help_text="Path to your PDT binary file." />
        </IshData>
    </IntegratedSensorHub>
    <Camera>
        <IPUSecurity label="IPU Security Configuration">
            <SecureTouch value="Disabled" value_list="Disabled,,Enabled" label="Secure Touch" help_text="When set, CAMERA_MASK register bits per CSI port are used to mask the data of cameras. When cleared, camera data is not masked. " />
            <FWSecureMode value="Enabled" value_list="Disabled,,Enabled" label="FW Secure Mode" help_text="If enabled, access blockers in IS and PS are enabled, and FW is read from IMR. Must be enabled for FW authentication flow and execution of authenticated FW." />
            <SecureTouchCameraMask value="0xFF" label="Secure Touch and Camera Mask" help_text="Camera mask bits per CSI port. When SECURE_TOUCH is set each set bit masks a CSI port for secure touch. When SECURE_TOUCH is cleared this register has no impact on the CSI ports." />
            <SWDriverControlsPortConfiguration value="Enabled" value_list="Disabled,,Enabled" label="SW Driver Controls Port Configuration " help_text="When set, port config is taken from the value IPU driver configures in IPU. When cleared, port config is taken from: CSI2_PORT_CONFIG_MSB.PORT_ID and CSI2_PORT_CONFIG_LSB.PORT_ID" />
        </IPUSecurity>
        <IPUDebug label="IPU Debug">
            <RomTraceEnable value="Enabled" value_list="Disabled,,Enabled" label="IPU Debugging Enabled" help_text="If enabled, IPU Debugging is enabled, otherwise internal setup is checked to see if the IPU Debugging feature should be enabled or not." />
        </IPUDebug>
        <IPUPhy label="IPU PHY">
            <PortConfigurationFor8LSBLanes value="0x0000" label="Port Configuration For 8 LSB Lanes" help_text="When CSI2_CNL.CR_OVRD  is cleared this determines the port configuration mapping between the lower 8 MIPI lanes and the CSI receiver ports the lanes can connect to:          Bits[3:0] determine the configuration of Port A:           0x0: port is disabled            0x4: X1 (ICL only)           0x5: X2 (ICL only)           Others: reserved            Bits[8:4] determine the configuration of Port B:            0x0: port is disabled            Others: reserved           Bits[10:9] determine the configuration of Port C:            0x0: port is disabled            0x2: X1            Others: reserved           Bits[13:11] determine the configuration of Port D:            0x0: port is disabled            0x5: X2            0x7: X4            Others: reserved" />
            <PortConfigurationFor8MSBLanes value="0x0000" label="Port Configuration For 8 MSB Lanes" help_text="When CSI2_CNL.CR_OVRD  is cleared this determines the port configuration mapping between the upper 8 MIPI lanes and the CSI receiver ports the lanes can connect to:           Bits[3:0] determine the configuration of Port A:            0x0: port is disabled            0x4: X1            0x5: X2            Others: reserved           Bits[8:4] determine the configuration of Port B:            0x0: port is disabled            0x9: X2            Others: reserved           Bits[10:9] determine the configuration of Port C:            0x0: port is disabled            0x2: X1            Others: reserved           Bits[13:11] determine the configuration of Port D:            0x0: port is disabled            0x5: X2            0x7: X4            Others: reserved" />
        </IPUPhy>
    </Camera>
    <Debug>
        <Idlm label="IDLM">
            <IdlmFile value="" label="IDLM Binary" help_text="This allows an IDLM binary to be merged into output image built by Intel (R) FIT" />
        </Idlm>
        <DelayedAuthenticationModeConfiguration label="Delayed Authentication Mode Configuration">
            <DelayedAuthMode value="No" value_list="No,,Yes" label="Delayed Authentication Mode Enabled" help_text="This setting enables Delayed Authentication Mode on the platform." />
        </DelayedAuthenticationModeConfiguration>
        <IntelTraceHubTechnology label="Intel(R) Trace Hub Technology">
            <IntelTrcHubBinary value="D:\Software Programmer Sept 2025\Bios Software\Flash Image Tool\Flash Image Tool 14.0.60.1790\WIN32\20251214_171950_XM25QH256B\Decomp\IntelTrcHubBinary.bin" label="Intel(R) Trace Hub Binary" help_text="This loads the Intel(R) Trace Hub binary that will be merged into the output image generated by the Intel(R) FIT tool." />
            <RomTraceEmergencyModeEn value="No" value_list="No,,Yes" label="Intel(R) Trace Hub Emergency Mode Enabled" help_text="When enabled, Intel(R) ME programs Intel(R) Trace hub to send debug traces without target configuration from the Intel(R) System Studio tool.   Note: When Intel(R) Trace Hub is enabled to send messages, it might prevent the system from entering deeper sleep states. This is intended for debug purposes only and should not be used in &quot;the&quot; shipping configuration." />
            <RomTraceFiltering value="D:\Software Programmer Sept 2025\Bios Software\Flash Image Tool\Flash Image Tool 14.0.60.1790\WIN32\20251214_171950_XM25QH256B\Decomp\RomTraceFiltering.bin" label="Intel(R) Trace Hub Filtering" help_text="This setting allows a user input binary for filtering of output messages for Intel(R) Trace Hub" />
            <RomTraceDbgMsgsEnable value="Yes" value_list="No,,Yes" label="Intel(R) Trace Hub Debug Messages Enabled" help_text="Intel(R) Trace Hub Debug Messages Enabled - When set to Yes, enables Intel(R) PCH HW trace messages.   Note: DCI needs to be enabled on the platform for Intel(R) Trace Hub messages to be captured." />
            <UnlockToken value="D:\Software Programmer Sept 2025\Bios Software\Flash Image Tool\Flash Image Tool 14.0.60.1790\WIN32\20251214_171950_XM25QH256B\Decomp\UnlockToken.bin" label="Unlock Token" help_text="This allows the OEM to input an Unlock Token binary file for closed chassis debug." />
        </IntelTraceHubTechnology>
        <IntelMeFirmwareDebuggingOverrides label="Intel(R) ME Firmware Debugging Overrides">
            <DbgOverridePreProdSi value="0x00000000" label="Debug Override Pre-Production Silicon" help_text="Allows the OEM to control FW features to assist with pre-production platform debugging.  This control has no effect if used on production silicon.  Note: Certain options will do not work when the descriptor is locked (See FW Bring-up Guide for setting details)." />
            <DbgOverrideProdSi value="0x00000000" label="Debug Override Production Silicon" help_text="Allows the OEM to control FW features to assist with production platform debugging.  Note: Certain options will do not work when the descriptor is locked (See FW Bring-up Guide for setting details)." />
            <MeRstBehavior value="Intel(R) ME will Halt" value_list="Intel(R) ME Alternate image boot,,Intel(R) ME will Halt" label="Intel(R) ME Reset Behavior" help_text="This setting determines Intel(R) ME behavior when boot image errors are encountered.  Warning: This setting should be used for debug purposes only.   Note: This may block normal Firmware functional flows ." />
            <MERomBypassEnable value="No" value_list="No,,Yes" label="Firmware ROM Bypass" help_text="This setting enables / disables firmware ROM bypass. Note: This setting only has affect when the firmware being used has ROM Bypass code present." />
            <AfsIdleReclaim value="Yes" value_list="Yes,,No" label="AFS Idle Flash Reclaim Enabled" help_text="This controls enabling / disabling of Intel(R) ME AFS Idle flash reclaim capabilities.   Note: This setting should be used for debug purposes only." />
        </IntelMeFirmwareDebuggingOverrides>
        <DirectConnectInterfaceConfiguration label="Direct Connect Interface Configuration">
            <DciEnable value="No" value_list="No,,Yes" label="Direct Connect Interface (DCI) Enabled" help_text="This setting enables / disables the DCI interface used for Intel(R) Trace Hub debugging." />
            <Usb1DciBssbEnable value="No" value_list="Yes,,No" label="DCI BSSB over USB3 Port1 Enabled" help_text="This setting determines if the USB port being used for DCI operations has BSSB (Boundary Scan Side Band) enabled.  Note: For S0ix and reset flows BSSB should be enabled.  Note: This setting will be grayed out if USB3 / PCIe Combo Port 0 under the Flex I/O tab is set to 'PCIe (or GbE)'" />
            <Usb2DciBssbEnable value="No" value_list="Yes,,No" label="DCI BSSB over USB3 Port2 Enabled" help_text="This setting determines if the USB port being used for DCI operations has BSSB (Boundary Scan Side Band) enabled.  Note: For S0ix and reset flows BSSB should be enabled.  Note: This setting will be grayed out if USB3 / PCIe Combo Port 1 under the Flex I/O tab is set to 'PCIe (or GbE)'" />
            <Usb3DciBssbEnable value="No" value_list="Yes,,No" label="DCI BSSB over USB3 Port3 Enabled" help_text="This setting determines if the USB port being used for DCI operations has BSSB (Boundary Scan Side Band) enabled.  Note: For S0ix and reset flows BSSB should be enabled.  Note: This setting will be grayed out if USB3 / PCIe Combo Port 2 under the Flex I/O tab is set to 'PCIe (or GbE)'" />
            <Usb4DciBssbEnable value="No" value_list="Yes,,No" label="DCI BSSB over USB3 Port4 Enabled" help_text="This setting determines if the USB port being used for DCI operations has BSSB (Boundary Scan Side Band) enabled.  Note: For S0ix and reset flows BSSB should be enabled.  Note: This setting will be grayed out if USB3 / PCIe Combo Port 3 under the Flex I/O tab is set to 'PCIe (or GbE)'" />
            <Usb5DciBssbEnable value="No" value_list="Yes,,No" label="DCI BSSB over USB3 Port5 Enabled" help_text="This setting determines if the USB port being used for DCI operations has BSSB (Boundary Scan Side Band) enabled.  Note: For S0ix and reset flows BSSB should be enabled.  Note: This setting will be grayed out if USB3 / PCIe Combo Port 4 under the Flex I/O tab is set to 'PCIe (or GbE)'" />
            <Usb6DciBssbEnable value="No" value_list="Yes,,No" label="DCI BSSB over USB3 Port6 Enabled" help_text="This setting determines if the USB port being used for DCI operations has BSSB (Boundary Scan Side Band) enabled.  Note: For S0ix and reset flows BSSB should be enabled.  Note: This setting will be grayed out if USB3 / PCIe Combo Port 5 under the Flex I/O tab is set to 'PCIe (or GbE)'" />
            <GPIODciBssbEnable value="No" value_list="Yes,,No" label="DCI BSSB over GPIO Enabled" help_text="This setting enables BSSB (Boundary Scan Side Band) over GPIO for DCI operations.  Note: If this setting is enabled the DCI BSSB over USB3 Port1 Enabled also needs to be set to 'Yes'.  Note:For S0ix and reset flows BSSB should be enabled." />
        </DirectConnectInterfaceConfiguration>
        <EspiFeatureOverrides label="eSPI Feature Overrides">
            <EspiEcLowFreqOvrd value="No" value_list="Yes,,No" label="eSPI / EC Low Frequency Debug Override" help_text="When enabled this setting will divide eSPI clock frequency by 8.  Note: This setting should only be used for debugging purposes. Leaving this setting enable will impact eSPI performance." />
        </EspiFeatureOverrides>
        <EarlyUsb2DbcOverType-AConfiguration label="Early USB2 DBC over Type-A Configuration">
            <MeBootStallEn value="No Boot Stall" value_list="No Boot Stall,,Boot Stall" label="Intel(R) ME Boot Stall Enabled" help_text="This setting enables a delay during Intel(R) ME FW bring-up to allow USB DCI to be established and Early DbC arbitration to be granted." />
            <Usb2DbcPortEn value="No USB3 Ports" value_list="USB2 Port 1,,USB2 Port 2,,USB2 Port 3,,USB2 Port 4,,USB2 Port 5,,USB2 Port 6,,USB2 Port 7,,USB2 Port 8,,USB2 Port 9,,USB2 Port 10,,No USB3 Ports" label="USB2 DbC port enable" help_text="This setting determines which USB2 ports are enabled for Early DbC debugging." />
            <Usb3DbcPortEn value="No USB3 Ports" value_list="USB3 Port 1,,USB3 Port 2,,USB3 Port 3,,USB3 Port 4,,USB3 Port 5,,USB3 Port 6,,No USB3 Ports" label="USB Connectors Associated USB3 Port enable" help_text="This setting determines which USB3 port goes to the target USB2 ports connector for Early DbC debugging." />
        </EarlyUsb2DbcOverType-AConfiguration>
    </Debug>
    <CpuStraps label="CPU Straps">
        <HyperThreadingDisable value="No" value_list="No,,Yes" label="Disable Hyperthreading" help_text="This setting control enabling / disabling of Hyper threading.  Note: This strap is intended for debugging purposed only. See BIOS Spec for more details on enabling / disabling Hyper threading" />
        <NumActiveCores value="All Cores Active" value_list="All Cores Active,,1 Core Active,,2 Cores Active,,3 Cores Active,,4 Cores Active,,5 Cores Active" label="Number of Active Cores" help_text="This setting controls the number of active processor cores.  Note: This strap is intended for debugging purposed only. See BIOS Spec for more details on enabling / disabling processor cores." />
        <BistInit value="No" value_list="No,,Yes" label="BIST Initialization" help_text="This setting determines if BIST will be run at platform reset after BIOS requested actions.  Note: This strap is intended for debugging purposed only." />
        <FlexRatio value="0x00000000" label="Flex Ratio" help_text="This setting controls the maximum processor non-turbo ratio.  Note: This strap is intended for debugging purposed only. See BIOS Spec for more details on maximum processor non-turbo ratio configuration." />
        <CpuMaxFreqBoot value="Yes" value_list="No,,Yes" label="Processor Boot Max Frequency" help_text="This setting determines if the processor will operate at maximum frequency at power-on and boot.  Note: This strap is intended for debugging purposed only." />
        <JtagPwrDisable value="No JTAG Power on C10 and Lower" value_list="No JTAG Power on C10 and Lower,,JTAG Power on C10 and Lower" label="JTAG Power Disable" help_text="This setting determines if JTAG power will be maintained on C10 or lower power states.  Note: This strap is intended for debugging purposed only." />
        <SaVrType value="SVID" value_list="SVID,,Fixed VR" label="SA VR Type" help_text="This setting determines the SA domain VR type.  Note: This setting should be set to &quot;Fixed VR&quot; for Desktop and &quot;SVID&quot; for Mobile" />
        <IaVrType value="SVID" value_list="SVID,,Fixed VR" label="IA Power Plane VR" help_text="This setting determines the IA core domain VR type." />
        <RingVrType value="SVID" value_list="SVID,,Fixed VR" label="Ring VR Type" help_text="This setting determines the Ring domain VR type. Note: This setting must match the IA VR setting." />
        <GtUsVrType value="SVID" value_list="SVID,,Fixed VR" label="GT_US VR Type" help_text="This setting determines the GT Unslice domain VR type." />
        <SvidPresence value="SVID is present" value_list="SVID is present,,SVID is not present" label="SVID Presence" help_text="This setting determine if SVID rails are present on the platform. This setting is for debugging purposes only." />
        <PlatformImonDisable value="Enabled" value_list="Enabled,,Disabled" label="Platform IMON" help_text="This strap should be left at the recommended default setting." />
        <GtsVrType value="SVID" value_list="SVID,,Fixed VR" label="GT_S VR Type" help_text="This setting determines the GT slice domain VR type." />
        <IaVrOffsetVid value="No" value_list="No,,Yes" label="IA SVID VR Offset Enabled" help_text="Enables/disables a voltage offset for the IA VR allowing voltage levels to exceed 1.52V.  The setting should always be set to Enabled." />
        <GtsSvidAddress value="0x00000001" label="GT_S SVID Address" help_text="This setting determines the GT slice SVID Address." />
        <GtUsSvidAddress value="0x00000001" label="GT_US SVID Address" help_text="This setting determines the GT Unslice SVID Address. Note: This strap should be left at the recommended default setting." />
        <RingSvidAddress value="0x00000000" label="Ring SVID Address" help_text="This setting determines the Ring SVID address. Note: This setting must match the IA VR setting." />
        <IaSvidAddress value="0x00000000" label="IA SVID Address" help_text="This setting determines the IA SVID address.   Note: This strap should be left at the recommended default setting." />
        <SaSvidAddress value="0x00000002" label="SA SVID Address" help_text="This setting determines the SA SVID address. Note: This strap should be left at the recommended default setting." />
    </CpuStraps>
    <StrapsDifferences>
        <PCH_Strap_SPI_touch2_max_freq_Diff value="0x00000003" />
        <PCH_Strap_SPI_cs1_max_io_mode_Diff value="0x00000003" />
        <PCH_Strap_CSME_CSE_Reserved_30_25_Strp_98_Diff value="0x00000000" />
        <PCH_Strap_CSME_CLINK_ON_DIE_CLINK_SELECT_Diff value="0x00000000" />
        <PCH_Strap_CSME_CLINK_CLINK_ENABLE_Diff value="0x00000000" />
        <PCH_Strap_PN2_RPCFG_0_Diff value="0x00000000" />
        <PCH_Strap_EXI_PTSS_PORT14_Diff value="0x00000001" />
        <PCH_Strap_EXI_PTSS_PORT13_Diff value="0x00000001" />
        <PCH_Strap_EXI_PTSS_PORT10_Diff value="0x00000001" />
        <PCH_Strap_EXI_PTSS_PORT9_Diff value="0x00000001" />
        <PCH_Strap_EXI_PTSS_PORT3_Diff value="0x00000001" />
        <PCH_Strap_EXI_PTSS_PORT1_Diff value="0x00000001" />
        <PCH_Strap_GBE_Xtal_clk_frequency_Diff value="0x00000001" />
        <PMC_Strap_CNVI_1P8_LDO_EN_Diff value="0x00000000" />
        <PMC_Strap_PECI_DIS_STRAP_Diff value="0x00000001" />
        <PMC_Strap_SMT6_DIS_STRAP_Diff value="0x00000001" />
        <PMC_Strap_SMT5_DIS_STRAP_Diff value="0x00000001" />
        <PMC_Strap_SMT4_DIS_STRAP_Diff value="0x00000001" />
        <PMC_Strap_GBEPHY_SMBUS_ADDR_Diff value="0x00000064" />
    </StrapsDifferences>
    <FlexIO label="Flex I/O">
        <IntelRstForPcieConfiguration label="Intel(R) RST for PCIe Configuration">
            <PCIeCtrl3Port1SrisEnable value="No" value_list="No,,Yes" label="PCIe Controller 3 Port 1 SRIS Enabled" help_text="This is used to configure SRIS Port 1 for Intel(R) RST for PCIe on PCIe Controller 3.  Note: Configuration of this setting is only required if the NVM device will be connected external SATA Express cable." />
            <PCIeCtrl3Port2SrisEnable value="No" value_list="No,,Yes" label="PCIe Controller 3 Port 2 SRIS Enabled" help_text="This is used to configure SRIS Port 2 for Intel(R) RST for PCIe on PCIe Controller 3.  Note: Configuration of this setting is only required if the NVM device will be connected external SATA Express cable." />
            <PCIeCtrl3Port3SrisEnable value="No" value_list="No,,Yes" label="PCIe Controller 3 Port 3 SRIS Enabled" help_text="This is used to configure SRIS Port 1 for Intel(R) RST for PCIe on PCIe Controller 3.  Note: Configuration of this setting is only required if the NVM device will be connected external SATA Express cable." />
            <PCIeCtrl3Port4SrisEnable value="No" value_list="No,,Yes" label="PCIe Controller 3 Port 4 SRIS Enabled" help_text="This is used to configure SRIS Port 4 for Intel(R) RST for PCIe on PCIe Controller 3.  Note: Configuration of this setting is only required if the NVM device will be connected external SATA Express cable." />
            <PCIeCtrl4Port1SrisEnable value="No" value_list="No,,Yes" label="PCIe Controller 4 Port 1 SRIS Enabled" help_text="This is used to configure SRIS Port 1 for Intel(R) RST for PCIe on PCIe Controller 4.  Note: Configuration of this setting is only required if the NVM device will be connected external SATA Express cable." />
            <PCIeCtrl4Port2SrisEnable value="No" value_list="No,,Yes" label="PCIe Controller 4 Port 2 SRIS Enabled" help_text="This is used to configure SRIS Port 2 for Intel(R) RST for PCIe on PCIe Controller 4.  Note: Configuration of this setting is only required if the NVM device will be connected external SATA Express cable." />
            <PCIeCtrl4Port3SrisEnable value="No" value_list="No,,Yes" label="PCIe Controller 4 Port 3 SRIS Enabled" help_text="This is used to configure SRIS Port 3 for Intel(R) RST for PCIe on PCIe Controller 4.  Note: Configuration of this setting is only required if the NVM device will be connected external SATA Express cable." />
            <PCIeCtrl4Port4SrisEnable value="No" value_list="No,,Yes" label="PCIe Controller 4 Port 4 SRIS Enabled" help_text="This is used to configure SRIS Port 4 for Intel(R) RST for PCIe on PCIe Controller 4.  Note: Configuration of this setting is only required if the NVM device will be connected external SATA Express cable." />
            <RstPCIe1C2Select value="x2" value_list="x2,,x4" label="Intel(R) RST for PCIe-C2 Select x2 or x4" help_text="This is used to configure NAND Cycle routers for the Intel(R) RST for PCIe interface as either x2 or x4 lane operation on PCIe Controller 3 [LP].  Note: This setting must match port configuration settings of Intel(R) RST for PCIe Controller 2 and PCIe Controller 3 [LP]." />
            <RstPCIe1C3Select value="x4" value_list="x2,,x4" label="Intel(R) RST for PCIe-C3 Select x2 or x4" help_text="This is used to configure NAND Cycle routers for the Intel(R) RST for PCIe interface as either x2 or x4 lane operation on PCIe Controller 4 [LP] or PCIe Controller 5 [S / H].  Note: This setting must match port configuration settings of Intel(R) RST for PCIe Controller 3 and PCIe Controller 4 [LP] or PCIe Controller 5 [S / H]." />
            <RstPCIeController2 value="2x2" value_list="2x2,,1x4" label="Intel® RST for PCIe Controller 2" help_text="This is used to configure PCIe Controller 2 for Intel(R) RST for PCIe interface as either x2 or x4 lane operation on PCIe Controller 3 [LP].  Note: This setting must match port configuration settings of Intel(R) RST for PCIe-C2 Select x2 or x4 and PCIe Controller 3 [LP]." />
            <RstPCIeController3 value="1x4" value_list="2x2,,1x4" label="Intel® RST for PCIe Controller 3" help_text="This is used to configure PCIe Controller 3 for Intel(R) RST for PCIe interface as either x2 or x4 lane operation on PCIe Controller 4 [LP].  Note: This setting must match port configuration settings of Intel(R) RST for PCIe-C3 Select x2 or x4 and PCIe Controller 4 [LP]." />
        </IntelRstForPcieConfiguration>
        <PcieLaneReversalConfiguration label="PCIe Lane Reversal Configuration">
            <PCIeCtrl1LnReversal value="No" value_list="No,,Yes" label="PCIe Controller 1 Lane Reversal Enabled" help_text="This setting allows the PCIe lanes on Controller 1 to be reversed. For further details see Canonlake H / LP Platform Controller Hub EDS." />
            <PCIeCtrl2LnReversal value="No" value_list="No,,Yes" label="PCIe Controller 2 Lane Reversal Enabled" help_text="This setting allows the PCIe lanes on Controller 2 to be reversed. For further details see Canonlake H / LP Platform Controller Hub EDS." />
            <PCIeCtrl3LnReversal value="No" value_list="No,,Yes" label="PCIe Controller 3 Lane Reversal Enabled" help_text="This setting allows the PCIe lanes on Controller 3 to be reversed. For further details see Canonlake H / LP Platform Controller Hub EDS." />
            <PCIeCtrl4LnReversal value="Yes" value_list="No,,Yes" label="PCIe Controller 4 Lane Reversal Enabled" help_text="This setting allows the PCIe lanes on Controller 4 to be reversed. For further details see Canonlake H / LP Platform Controller Hub EDS." />
        </PcieLaneReversalConfiguration>
        <PciePortConfiguration label="PCIe Port Configuration">
            <PCIeContoller1Config value="4x1" value_list="4x1,,1x2, 2x1,,2x2,,1x4" label="PCIe Controller 1 (Port 1-4)" help_text="This setting controls PCIe Port configurations for PCIe Controller 1. For further details see Canonlake H / LP Platform Controller Hub EDS." />
            <PCIeContoller2Config value="4x1" value_list="4x1,,1x2, 2x1,,2x2,,1x4" label="PCIe Controller 2 (Port 5-8)" help_text="This setting controls PCIe Port configurations for PCIe Controller 2. For further details see Canonlake H / LP Platform Controller Hub EDS." />
            <PCIeContoller3Config value="4x1" value_list="4x1,,1x2, 2x1,,2x2,,1x4" label="PCIe Controller 3 (Port 9-12)" help_text="This setting controls PCIe Port configurations for PCIe Controller 3. For further details see Canonlake H / LP Platform Controller Hub EDS." />
            <PCIeContoller4Config value="1x4" value_list="4x1,,1x2, 2x1,,2x2,,1x4" label="PCIe Controller 4 (Port 13-16)" help_text="This setting controls PCIe Port configurations for PCIe Controller 4. For further details see Canonlake H / LP Platform Controller Hub EDS." />
        </PciePortConfiguration>
        <SataPcieComboPortConfiguration label="SATA / PCIe Combo Port Configuration">
            <SataPcieCombo0ModeSel value="PCIe CLKREQ#" value_list="PCIe CLKREQ#,,DEVSLP#" label="SATA / PCIe Combo Port 0 Mode Select" help_text="The corresponding CLKREQ# GPIO can only function as DEVSLP# if SATA / PCIe Combo Port 0 is assigned to SATA, and SATA / PCIe Combo Port 0 Mode Select is configured to SATA  DEVSLP#." />
            <SataPcieCombo1ModeSel value="PCIe CLKREQ#" value_list="PCIe CLKREQ#,,DEVSLP#" label="SATA / PCIe Combo Port 1 Mode Select" help_text="The corresponding CLKREQ# GPIO can only function as DEVSLP# if SATA / PCIe Combo Port 1 is assigned to SATA, and SATA / PCIe Combo Port 1 Mode Select is configured to SATA  DEVSLP#." />
            <SataPcieCombo2ModeSel value="PCIe CLKREQ#" value_list="PCIe CLKREQ#,,DEVSLP#" label="SATA / PCIe Combo Port 2 Mode Select" help_text="The corresponding CLKREQ# GPIO can only function as DEVSLP# if SATA / PCIe Combo Port 2 is assigned to SATA, and SATA / PCIe Combo Port 2 Mode Select is configured to SATA  DEVSLP#." />
            <SataPCIeComboPort0 value="SATA" value_list="GPIO Polarity PCIe,,GPIO Polarity SATA,,SATA,,PCIe" label="SATA / PCIe Combo Port 0" help_text="This setting configures the PCIe port to operate as either PCIe Port 11 or SATA Port 0.  For further details on Flex I/O see Canonlake LP Platform Controller Hub EDS.  Note: For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA, the lanes must be statically assigned to SATA or PCIe*. These unused SATA/PCIe* Combo Lanes must not be assigned as polarity based." />
            <SataPCIeComboPort1 value="GPIO Polarity SATA" value_list="GPIO Polarity PCIe,,GPIO Polarity SATA,,SATA,,PCIe" label="SATA / PCIe Combo Port 1" help_text="This setting configures the PCIe port to operate as either PCIe Port 12 or SATA Port 1. For further details on Flex I/O see Canonlake LP Platform Controller Hub EDS.   Note: For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA, the lanes must be statically assigned to SATA or PCIe*. These unused SATA/PCIe* Combo Lanes must not be assigned as polarity based." />
            <SataPCIeComboPort2 value="PCIe" value_list="GPIO Polarity PCIe,,GPIO Polarity SATA,,SATA,,PCIe" label="SATA / PCIe Combo Port 2" help_text="This setting configures the PCIe port to operate as either PCIe Port 15 or SATA Port 1. For further details on Flex I/O see Canonlake LP Platform Controller Hub EDS.   Note: For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA, the lanes must be statically assigned to SATA or PCIe*. These unused SATA/PCIe* Combo Lanes must not be assigned as polarity based." />
            <SataPCIeComboPort3 value="GPIO Polarity PCIe" value_list="GPIO Polarity PCIe,,GPIO Polarity SATA,,SATA,,PCIe" label="SATA / PCIe Combo Port 3" help_text="This setting configures the PCIe port to operate as either PCIe Port 16 or SATA Port 2. For further details on Flex I/O see Canonlake LP Platform Controller Hub EDS.   For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA, the lanes must be statically assigned to SATA or PCIe*. These unused SATA/PCIe* Combo Lanes must not be assigned as polarity based." />
        </SataPcieComboPortConfiguration>
        <Usb3PortConfiguration label="USB3 Port Configuration">
            <USB3PCIeComboPort0 value="USB3" value_list="USB3,,PCIe" label="USB3 / PCIe Combo Port 0" help_text="This setting configures the PCIe port to operate as either PCIe Port 1 or USB3 Port 1.  For further details on Flex I/O see Canonlake LP Platform Controller Hub EDS.  Note: This setting will be grayed out if DCI BSSB over USB3 Port1 Enabled is set to 'yes'." />
            <USB3PCIeComboPort1 value="USB3" value_list="USB3,,PCIe" label="USB3 / PCIe Combo Port 1" help_text="This setting configures the PCIe port to operate as either PCIe Port 2 or USB3 Port 2. For further details on Flex I/O see Canonlake LP Platform Controller Hub EDS.  Note: This setting will be grayed out if DCI BSSB over USB3 Port2 Enabled is set to 'yes'." />
            <USB3PCIeComboPort2 value="USB3" value_list="USB3,,PCIe" label="USB3 / PCIe Combo Port 2" help_text="This setting configures the PCIe port to operate as either PCIe Port 3 or USB3 Port 3. For further details on Flex I/O see Canonlake LP Platform Controller Hub EDS.  Note: This setting will be grayed out if DCI BSSB over USB3 Port3 Enabled is set to 'yes'." />
            <USB3PCIeComboPort3 value="USB3" value_list="USB3,,PCIe" label="USB3 / PCIe Combo Port 3" help_text="This setting configures the PCIe port to operate as either PCIe Port 4 or USB3 Port 4. For further details on Flex I/O see Canonlake LP Platform Controller Hub EDS.  Note: This setting will be grayed out if DCI BSSB over USB3 Port4 Enabled is set to 'yes'." />
            <USB3PCIeComboPort4 value="USB3" value_list="USB3,,PCIe" label="USB3 / PCIe Combo Port 4" help_text="This setting configures the PCIe port to operate as either PCIe Port 5 or USB3 Port 5. For further details on Flex I/O see Canonlake LP Platform Controller Hub EDS.  Note: This setting will be grayed out if DCI BSSB over USB3 Port5 Enabled is set to 'yes'." />
            <USB3PCIeComboPort5 value="PCIe" value_list="USB3,,PCIe" label="USB3 / PCIe Combo Port 5" help_text="This setting configures the PCIe port to operate as either PCIe Port 6 or USB3 Port 6. For further details on Flex I/O see Canonlake LP Platform Controller Hub EDS.  Note: This setting will be grayed out if DCI BSSB over USB3 Port6 Enabled is set to 'yes'." />
            <USB3Prt1ConTypeSel value="Type A / Type C" value_list="Type C,,Type A / Type C,,Express Card / M.2 S2" label="USB3 Port 1 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB 3.0 / 3.1 Port 1." />
            <USB3Prt2ConTypeSel value="Type A / Type C" value_list="Type C,,Type A / Type C,,Express Card / M.2 S2" label="USB3 Port 2 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB 3.0 / 3.1 Port 2." />
            <USB3Prt3ConTypeSel value="Type A / Type C" value_list="Type C,,Type A / Type C,,Express Card / M.2 S2" label="USB3 Port 3 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB 3.0 / 3.1 Port 3." />
            <USB3Prt4ConTypeSel value="Type A / Type C" value_list="Type C,,Type A / Type C,,Express Card / M.2 S2" label="USB3 Port 4 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB 3.0 / 3.1 Port 4." />
            <USB3Prt5ConTypeSel value="Express Card / M.2 S2" value_list="Type C,,Type A / Type C,,Express Card / M.2 S2" label="USB3 Port 5 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB 3.0 / 3.1 Port 5." />
            <USB3Prt6ConTypeSel value="Type A / Type C" value_list="Type C,,Type A / Type C,,Express Card / M.2 S2" label="USB3 Port 6 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB 3.0 / 3.1 Port 6." />
            <USB3Port1IntSpdSel value="USB3.1 Gen1 LBPM" value_list="USB3.1 Gen1 LBPM,,USB3.1 Gen2 Skip LBPM" label="USB3 Port 1 Initialization Speed Select" help_text="This setting determines USB3 Port 1 speed during platform power-up.   Note: When configured to USB 3.1 Gen1 the port will also preform carry on LBPM if USB 3.1 is Gen2 enabled." />
            <USB3Port2IntSpdSel value="USB3.1 Gen1 LBPM" value_list="USB3.1 Gen1 LBPM,,USB3.1 Gen2 Skip LBPM" label="USB3 Port 2 Initialization Speed Select" help_text="This setting determines USB3 Port 2 speed during platform power-up.   Note: When configured to USB 3.1 Gen1 the port will also preform carry on LBPM if USB 3.1 is Gen2 enabled." />
            <USB3Port3IntSpdSel value="USB3.1 Gen1 LBPM" value_list="USB3.1 Gen1 LBPM,,USB3.1 Gen2 Skip LBPM" label="USB3 Port 3 Initialization Speed Select" help_text="This setting determines USB3 Port 3 speed during platform power-up.   Note: When configured to USB 3.1 Gen1 the port will also preform carry on LBPM if USB 3.1 is Gen2 enabled." />
            <USB3Port4IntSpdSel value="USB3.1 Gen1 LBPM" value_list="USB3.1 Gen1 LBPM,,USB3.1 Gen2 Skip LBPM" label="USB3 Port 4 Initialization Speed Select" help_text="This setting determines USB3 Port 4 speed during platform power-up.   Note: When configured to USB 3.1 Gen1 the port will also preform carry on LBPM if USB 3.1 is Gen2 enabled." />
            <USB3Port5IntSpdSel value="USB3.1 Gen1 LBPM" value_list="USB3.1 Gen1 LBPM,,USB3.1 Gen2 Skip LBPM" label="USB3 Port 5 Initialization Speed Select" help_text="This setting determines USB3 Port 5 speed during platform power-up.   Note: When configured to USB 3.1 Gen1 the port will also preform carry on LBPM if USB 3.1 is Gen2 enabled." />
            <USB3Port6IntSpdSel value="USB3.1 Gen1 LBPM" value_list="USB3.1 Gen1 LBPM,,USB3.1 Gen2 Skip LBPM" label="USB3 Port 6 Initialization Speed Select" help_text="This setting determines USB3 Port 6 speed during platform power-up.   Note: When configured to USB 3.1 Gen1 the port will also preform carry on LBPM if USB 3.1 is Gen2 enabled." />
            <USB3Port1SpdCap value="USB 3.1 Gen2" value_list="USB 3.1 Gen1,,USB 3.1 Gen2" label="USB3 Port 1 Speed Capability" help_text="This setting determines the USB3 Port 1 speed capabilities." />
            <USB3Port2SpdCap value="USB 3.1 Gen1" value_list="USB 3.1 Gen1,,USB 3.1 Gen2" label="USB3 Port 2 Speed Capability" help_text="This setting determines the USB3 Port 2 speed capabilities." />
            <USB3Port3SpdCap value="USB 3.1 Gen1" value_list="USB 3.1 Gen1,,USB 3.1 Gen2" label="USB3 Port 3 Speed Capability" help_text="This setting determines the USB3 Port 3 speed capabilities." />
            <USB3Port4SpdCap value="USB 3.1 Gen1" value_list="USB 3.1 Gen1,,USB 3.1 Gen2" label="USB3 Port 4 Speed Capability" help_text="This setting determines the USB3 Port 4 speed capabilities." />
            <USB3Port5SpdCap value="USB 3.1 Gen1" value_list="USB 3.1 Gen1,,USB 3.1 Gen2" label="USB3 Port 5 Speed Capability" help_text="This setting determines the USB3 Port 5 speed capabilities." />
            <USB3Port6SpdCap value="USB 3.1 Gen1" value_list="USB 3.1 Gen1,,USB 3.1 Gen2" label="USB3 Port 6 Speed Capability" help_text="This setting determines the USB3 Port 6 speed capabilities." />
            <UsbTypeAbModeSel value="USB Type AB SW Select" value_list="USB Type AB SW Select,,USB Type AB HW Select" label="USB Type AB Mode Select" help_text="This setting determines how the USB Type AB connector switching is handled." />
        </Usb3PortConfiguration>
        <Usb2PortConfiguration label="USB2 Port Configuration">
            <USB2Prt1ConTypeSel value="Type A / Type C" value_list="Type C,,Type A / Type C,,Express Card / M.2 S2" label="USB2 Port 1 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 1." />
            <USB2Prt2ConTypeSel value="Type A / Type C" value_list="Type C,,Type A / Type C,,Express Card / M.2 S2" label="USB2 Port 2 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 2." />
            <USB2Prt3ConTypeSel value="Type A / Type C" value_list="Type C,,Type A / Type C,,Express Card / M.2 S2" label="USB2 Port 3 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 3." />
            <USB2Prt4ConTypeSel value="Type A / Type C" value_list="Type C,,Type A / Type C,,Express Card / M.2 S2" label="USB2 Port 4 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 4." />
            <USB2Prt5ConTypeSel value="Type A / Type C" value_list="Type C,,Type A / Type C,,Express Card / M.2 S2" label="USB2 Port 5 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 5." />
            <USB2Prt6ConTypeSel value="Type A / Type C" value_list="Type C,,Type A / Type C,,Express Card / M.2 S2" label="USB2 Port 6 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 6." />
            <USB2Prt7ConTypeSel value="Express Card / M.2 S2" value_list="Type C,,Type A / Type C,,Express Card / M.2 S2" label="USB2 Port 7 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 7." />
            <USB2Prt8ConTypeSel value="Type A / Type C" value_list="Type C,,Type A / Type C,,Express Card / M.2 S2" label="USB2 Port 8 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 8." />
            <USB2Prt9ConTypeSel value="Type A / Type C" value_list="Type C,,Type A / Type C,,Express Card / M.2 S2" label="USB2 Port 9 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 9." />
            <USB2Prt10ConTypeSel value="Express Card / M.2 S2" value_list="Type C,,Type A / Type C,,Express Card / M.2 S2" label="USB2 Port 10 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 10." />
        </Usb2PortConfiguration>
    </FlexIO>
    <Gpio label="GPIO">
        <MeFeaturePins label="ME Feature Pins">
            <TouchResetGpio value="None" value_list="None,,GPP_A_0,,GPP_A_1,,GPP_A_2,,GPP_A_3,,GPP_A_4,,GPP_A_5,,GPP_A_6,,GPP_A_7,,GPP_A_8,,GPP_A_9,,GPP_A_10,,GPP_A_11,,GPP_A_13,,GPP_A_14,,GPP_A_15,,GPP_A_16,,GPP_A_17,,GPP_A_18,,GPP_A_19,,GPP_A_20,,GPP_A_21,,GPP_A_22,,GPP_A_23,,GPP_B_0,,GPP_B_1,,GPP_B_2,,GPP_B_3,,GPP_B_4,,GPP_B_5,,GPP_B_6,,GPP_B_7,,GPP_B_8,,GPP_B_9,,GPP_B_10,,GPP_B_11,,GPP_B_12,,GPP_B_13,,GPP_B_14,,GPP_B_15,,GPP_B_16,,GPP_B_17,,GPP_B_18,,GPP_B_19,,GPP_B_20,,GPP_B_21,,GPP_B_22,,GPP_B_23,,GPP_C_0,,GPP_C_1,,GPP_C_2,,GPP_C_3,,GPP_C_4,,GPP_C_5,,GPP_C_6,,GPP_C_7,,GPP_C_8,,GPP_C_9,,GPP_C_10,,GPP_C_11,,GPP_C_12,,GPP_C_13,,GPP_C_14,,GPP_C_15,,GPP_C_16,,GPP_C_17,,GPP_C_18,,GPP_C_19,,GPP_C_20,,GPP_C_21,,GPP_C_22,,GPP_C_23,,GPP_D_0,,GPP_D_1,,GPP_D_2,,GPP_D_3,,GPP_D_4,,GPP_D_5,,GPP_D_6,,GPP_D_7,,GPP_D_8,,GPP_D_9,,GPP_D_10,,GPP_D_11,,GPP_D_12,,GPP_D_13,,GPP_D_14,,GPP_D_15,,GPP_D_16,,GPP_D_17,,GPP_D_18,,GPP_D_19,,GPP_D_20,,GPP_D_23,,GPP_E_0,,GPP_E_1,,GPP_E_2,,GPP_E_3,,GPP_E_4,,GPP_E_5,,GPP_E_6,,GPP_E_7,,GPP_E_8,,GPP_E_9,,GPP_E_10,,GPP_E_11,,GPP_E_12,,GPP_E_13,,GPP_E_14,,GPP_E_15,,GPP_E_16,,GPP_E_17,,GPP_E_18,,GPP_E_19,,GPP_E_20,,GPP_E_21,,GPP_E_22,,GPP_E_23,,GPP_F_0,,GPP_F_1,,GPP_F_2,,GPP_F_3,,GPP_F_4,,GPP_F_5,,GPP_F_6,,GPP_F_7,,GPP_F_8,,GPP_F_9,,GPP_F_10,,GPP_F_11,,GPP_F_12,,GPP_F_13,,GPP_F_14,,GPP_F_15,,GPP_F_16,,GPP_F_17,,GPP_F_18,,GPP_F_19,,GPP_F_20,,GPP_F_21,,GPP_F_22,,GPP_F_23,,GPP_G_0,,GPP_G_1,,GPP_G_2,,GPP_G_3,,GPP_G_4,,GPP_G_5,,GPP_G_6,,GPP_G_7,,GPP_H_0,,GPP_H_1,,GPP_H_2,,GPP_H_3,,GPP_H_4,,GPP_H_5,,GPP_H_6,,GPP_H_7,,GPP_H_8,,GPP_H_9,,GPP_H_10,,GPP_H_11,,GPP_H_12,,GPP_H_13,,GPP_H_14,,GPP_H_15,,GPP_H_16,,GPP_H_17,,GPP_H_18,,GPP_H_19,,GPP_H_20,,GPP_H_21,,GPP_H_22,,GPP_H_23,,GPD_0,,GPD_1,,GPD_2,,GPD_3,,GPD_4,,GPD_5,,GPD_6,,GPD_7,,GPD_8,,GPD_9,,GPD_10,,GPD_11" label="Intel(R) Precise Touch and Stylus Reset GPIO Select" help_text="Configure Intel(R) Precise Touch Technology Reset GPIO" />
            <TouchIntGpio value="None" value_list="None,,GPP_A_0,,GPP_A_1,,GPP_A_2,,GPP_A_3,,GPP_A_4,,GPP_A_5,,GPP_A_6,,GPP_A_7,,GPP_A_8,,GPP_A_9,,GPP_A_10,,GPP_A_11,,GPP_A_13,,GPP_A_14,,GPP_A_15,,GPP_A_16,,GPP_A_17,,GPP_A_18,,GPP_A_19,,GPP_A_20,,GPP_A_21,,GPP_A_22,,GPP_A_23,,GPP_B_0,,GPP_B_1,,GPP_B_2,,GPP_B_3,,GPP_B_4,,GPP_B_5,,GPP_B_6,,GPP_B_7,,GPP_B_8,,GPP_B_9,,GPP_B_10,,GPP_B_11,,GPP_B_12,,GPP_B_13,,GPP_B_14,,GPP_B_15,,GPP_B_16,,GPP_B_17,,GPP_B_18,,GPP_B_19,,GPP_B_20,,GPP_B_21,,GPP_B_22,,GPP_B_23,,GPP_C_0,,GPP_C_1,,GPP_C_2,,GPP_C_3,,GPP_C_4,,GPP_C_5,,GPP_C_6,,GPP_C_7,,GPP_C_8,,GPP_C_9,,GPP_C_10,,GPP_C_11,,GPP_C_12,,GPP_C_13,,GPP_C_14,,GPP_C_15,,GPP_C_16,,GPP_C_17,,GPP_C_18,,GPP_C_19,,GPP_C_20,,GPP_C_21,,GPP_C_22,,GPP_C_23,,GPP_D_0,,GPP_D_1,,GPP_D_2,,GPP_D_3,,GPP_D_4,,GPP_D_5,,GPP_D_6,,GPP_D_7,,GPP_D_8,,GPP_D_9,,GPP_D_10,,GPP_D_11,,GPP_D_12,,GPP_D_13,,GPP_D_14,,GPP_D_15,,GPP_D_16,,GPP_D_17,,GPP_D_18,,GPP_D_19,,GPP_D_20,,GPP_D_23,,GPP_E_0,,GPP_E_1,,GPP_E_2,,GPP_E_3,,GPP_E_4,,GPP_E_5,,GPP_E_6,,GPP_E_7,,GPP_E_8,,GPP_E_9,,GPP_E_10,,GPP_E_11,,GPP_E_12,,GPP_E_13,,GPP_E_14,,GPP_E_15,,GPP_E_16,,GPP_E_17,,GPP_E_18,,GPP_E_19,,GPP_E_20,,GPP_E_21,,GPP_E_22,,GPP_E_23,,GPP_F_0,,GPP_F_1,,GPP_F_2,,GPP_F_3,,GPP_F_4,,GPP_F_5,,GPP_F_6,,GPP_F_7,,GPP_F_8,,GPP_F_9,,GPP_F_10,,GPP_F_11,,GPP_F_12,,GPP_F_13,,GPP_F_14,,GPP_F_15,,GPP_F_16,,GPP_F_17,,GPP_F_18,,GPP_F_19,,GPP_F_20,,GPP_F_21,,GPP_F_22,,GPP_F_23,,GPP_G_0,,GPP_G_1,,GPP_G_2,,GPP_G_3,,GPP_G_4,,GPP_G_5,,GPP_G_6,,GPP_G_7,,GPP_H_0,,GPP_H_1,,GPP_H_2,,GPP_H_3,,GPP_H_4,,GPP_H_5,,GPP_H_6,,GPP_H_7,,GPP_H_8,,GPP_H_9,,GPP_H_10,,GPP_H_11,,GPP_H_12,,GPP_H_13,,GPP_H_14,,GPP_H_15,,GPP_H_16,,GPP_H_17,,GPP_H_18,,GPP_H_19,,GPP_H_20,,GPP_H_21,,GPP_H_22,,GPP_H_23,,GPD_0,,GPD_1,,GPD_2,,GPD_3,,GPD_4,,GPD_5,,GPD_6,,GPD_7,,GPD_8,,GPD_9,,GPD_10,,GPD_11" label="Intel(R) Precise Touch and Stylus Interrupt GPIO Select" help_text="Configure Intel(R) Precise Touch Technology Interrupt GPIO" />
        </MeFeaturePins>
        <GpioVccioVoltageControl label="GPIO VCCIO Voltage Control">
            <GppA0voltSelect value="1.8Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A0 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A0 GPIO pin." />
            <GppA1voltSelect value="1.8Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A1 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A1 GPIO pin." />
            <GppA2voltSelect value="1.8Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A2 GPIO pin." />
            <GppA3voltSelect value="1.8Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A3 GPIO pin." />
            <GppA4voltSelect value="1.8Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A4 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A4 GPIO pin." />
            <GppA5voltSelect value="1.8Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A5 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A5 GPIO pin." />
            <GppA6voltSelect value="1.8Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A6 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A6 GPIO pin." />
            <GppA7voltSelect value="1.8Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A7 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A7 GPIO pin." />
            <GppA8voltSelect value="1.8Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A8 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A8 GPIO pin." />
            <GppA9voltSelect value="1.8Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A9 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A9 GPIO pin." />
            <GppA10voltSelect value="1.8Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A10 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A10 GPIO pin." />
            <GppA11voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A11 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A11 GPIO pin." />
            <GppA12voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A12 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A12 GPIO pin." />
            <GppA13voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A13 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A13 GPIO pin." />
            <GppA14voltSelect value="1.8Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A14 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A14 GPIO pin." />
            <GppA15voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A15 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A15 GPIO pin." />
            <GppA16voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A16 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A16 GPIO pin." />
            <GppA17voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A17 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A17 GPIO pin." />
            <GppA18voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A18 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A18 GPIO pin." />
            <GppA19voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A19 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A19 GPIO pin." />
            <GppA20voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A20 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A20 GPIO pin." />
            <GppA21voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A21 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A21 GPIO pin." />
            <GppA22voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A22 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A22 GPIO pin." />
            <GppA23voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_A23 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A23 GPIO pin." />
            <GppB0voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B0 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B0 GPIO pin." />
            <GppB1voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B1 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B1 GPIO pin." />
            <GppB2voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B2 GPIO pin." />
            <GppB3voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B3 GPIO pin." />
            <GppB4voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B4 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B4 GPIO pin." />
            <GppB5voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B5 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B5 GPIO pin." />
            <GppB6voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B6 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B6 GPIO pin." />
            <GppB7voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B7 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B7 GPIO pin." />
            <GppB8voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B8 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B8 GPIO pin." />
            <GppB9voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B9 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B9 GPIO pin." />
            <GppB10voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B10 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B10 GPIO pin." />
            <GppB11voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B11 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B11 GPIO pin." />
            <GppB12voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B12 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B12 GPIO pin." />
            <GppB13voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B13 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B13 GPIO pin." />
            <GppB14voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B14 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B14 GPIO pin." />
            <GppB15voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B15 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B15 GPIO pin." />
            <GppB16voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B16 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B16 GPIO pin." />
            <GppB17voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B17 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B17 GPIO pin." />
            <GppB18voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B18 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B18 GPIO pin." />
            <GppB19voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B19 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B19 GPIO pin." />
            <GppB20voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B20 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B20 GPIO pin." />
            <GppB21voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B21 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B21 GPIO pin." />
            <GppB22voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B22 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B22 GPIO pin." />
            <GppB23voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_B23 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B23 GPIO pin." />
            <GppC0voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C0 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C0 GPIO pin." />
            <GppC1voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C1 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C1 GPIO pin." />
            <GppC2voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C2 GPIO pin." />
            <GppC3voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C3 GPIO pin." />
            <GppC4voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C4 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C4 GPIO pin." />
            <GppC5voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C5 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C5 GPIO pin." />
            <GppC6voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C6 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C6 GPIO pin." />
            <GppC7voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C7 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C7 GPIO pin." />
            <GppC8voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C8 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C8 GPIO pin." />
            <GppC9voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C9 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C9 GPIO pin." />
            <GppC10voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C10 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C10 GPIO pin." />
            <GppC11voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C11 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C11 GPIO pin." />
            <GppC12voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C12 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C12 GPIO pin." />
            <GppC13voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C13 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C13 GPIO pin." />
            <GppC14voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C14 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C14 GPIO pin." />
            <GppC15voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C15 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C15 GPIO pin." />
            <GppC16voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C16 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C16 GPIO pin." />
            <GppC17voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C17 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C17 GPIO pin." />
            <GppC18voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C18 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C18 GPIO pin." />
            <GppC19voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C19 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C19 GPIO pin." />
            <GppC20voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C20 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C20 GPIO pin." />
            <GppC21voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C21 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C21 GPIO pin." />
            <GppC22voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C22 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C22 GPIO pin." />
            <GppC23voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_C23 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C23 GPIO pin." />
            <GppD0voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D0 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D0 GPIO pin." />
            <GppD1voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D1 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D1 GPIO pin." />
            <GppD2voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D2 GPIO pin." />
            <GppD3voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D3 GPIO pin." />
            <GppD4voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D4 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D4 GPIO pin." />
            <GppD5voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D5 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D5 GPIO pin." />
            <GppD6voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D6 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D6 GPIO pin." />
            <GppD7voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D7 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D7 GPIO pin." />
            <GppD8voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D8 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D8 GPIO pin." />
            <GppD9voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D9 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D9 GPIO pin." />
            <GppD10voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D10 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D10 GPIO pin." />
            <GppD11voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D11 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D11 GPIO pin." />
            <GppD12voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D12 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D12 GPIO pin." />
            <GppD13voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D13 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D13 GPIO pin." />
            <GppD14voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D14 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D14 GPIO pin." />
            <GppD15voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D15 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D15 GPIO pin." />
            <GppD16voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D16 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D16 GPIO pin." />
            <GppD17voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D17 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D17 GPIO pin." />
            <GppD18voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D18 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D18 GPIO pin." />
            <GppD19voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D19 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D19 GPIO pin." />
            <GppD20voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D20 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D20 GPIO pin." />
            <GppD21voltSelect value="1.8Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D21 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D21 GPIO pin." />
            <GppD22voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D22 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D22 GPIO pin." />
            <GppD23voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_D23 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D23 GPIO pin." />
            <GppE0voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E0 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E0 GPIO pin." />
            <GppE1voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E1 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E0 GPIO pin." />
            <GppE2voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E2 GPIO pin." />
            <GppE3voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E3 GPIO pin." />
            <GppE4voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E4 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E4 GPIO pin." />
            <GppE5voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E5 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E5 GPIO pin." />
            <GppE6voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E6 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E6 GPIO pin." />
            <GppE7voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E7 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E7 GPIO pin." />
            <GppE8voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E8 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E8 GPIO pin." />
            <GppE9voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E9 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E9 GPIO pin." />
            <GppE10voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E10 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E10 GPIO pin." />
            <GppE11voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E11 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E11 GPIO pin." />
            <GppE12voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E12 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E11 GPIO pin." />
            <GppE13voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E13 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E13 GPIO pin." />
            <GppE14voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E14 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E14 GPIO pin." />
            <GppE15voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E15 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E15 GPIO pin." />
            <GppE16voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E16 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E16 GPIO pin." />
            <GppE17voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E17 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E17 GPIO pin." />
            <GppE18voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E18 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E19 GPIO pin." />
            <GppE19voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E19 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E19 GPIO pin." />
            <GppE20voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E20 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E20 GPIO pin." />
            <GppE21voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E21 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E21 GPIO pin." />
            <GppE22voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E22 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E22 GPIO pin." />
            <GppE23voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_E23 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E23 GPIO pin." />
            <GppG0voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_G0 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_G0 GPIO pin." />
            <GppG1voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_G1 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_G1 GPIO pin." />
            <GppG2voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_G2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_G2 GPIO pin." />
            <GppG3voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_G3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_G3 GPIO pin." />
            <GppG4voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_G4 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_G4 GPIO pin." />
            <GppG5voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_G5 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_G5 GPIO pin." />
            <GppG6voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_G6 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_G6 GPIO pin." />
            <GppG7voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_G7 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_G7 GPIO pin." />
            <GppH0voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H0 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H0 GPIO pin." />
            <GppH1voltSelect value="1.8Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H1 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H1 GPIO pin." />
            <GppH2voltSelect value="1.8Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H2 GPIO pin." />
            <GppH3voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H3 GPIO pin." />
            <GppH4voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H4 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H4 GPIO pin." />
            <GppH5voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H5 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H5 GPIO pin." />
            <GppH6voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H6 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H6 GPIO pin." />
            <GppH7voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H7 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H7 GPIO pin." />
            <GppH8voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H8 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H8 GPIO pin." />
            <GppH9voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H9 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H9 GPIO pin." />
            <GppH10voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H10 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H10 GPIO pin." />
            <GppH11voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H11 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H11 GPIO pin." />
            <GppH12voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H12 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H12 GPIO pin." />
            <GppH13voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H13 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H13 GPIO pin." />
            <GppH14voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H14 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H14 GPIO pin." />
            <GppH15voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H15 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H15 GPIO pin." />
            <GppH16voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H16 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H16 GPIO pin." />
            <GppH17voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H17 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H17 GPIO pin." />
            <GppH18voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H18 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H18 GPIO pin." />
            <GppH19voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H19 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H19 GPIO pin." />
            <GppH20voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H20 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H20 GPIO pin." />
            <GppH21voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H21 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H21 GPIO pin." />
            <GppH22voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H22 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H22 GPIO pin." />
            <GppH23voltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="GPP_H23 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H23 GPIO pin." />
            <HdaVoltSelect value="3.3Volts" value_list="3.3Volts,,1.8Volts" label="Intel(R) HD Audio Voltage Select" help_text="The setting configures the VCCHDA pin voltage." />
        </GpioVccioVoltageControl>
    </Gpio>
    <IntelPreciseTouchAndStylus label="Intel(R) Precise Touch and Stylus">
        <IntegratedTouchConfiguration label="Intel(R) Precise Touch and Stylus Configuration">
            <TouchEnabled value="No" value_list="No,,Yes" label="Intel(R) Precise Touch and Stylus Enabled" />
        </IntegratedTouchConfiguration>
        <IntelPreciseTouchAndStylusConfiguration label="Intel(R) Precise Touch and Stylus Configuration">
            <Touch1MaxFreq value="30MHz" value_list="17MHz,,30MHz" label="Intel(R) Precise Touch and Stylus Controller 1 Maximum Frequency" help_text="This setting allows customers to set an upper limit on the frequency for Intel(R) Precise Touch and Stylus transactions for the Touch Controller 1 interface." />
        </IntelPreciseTouchAndStylusConfiguration>
    </IntelPreciseTouchAndStylus>
    <FWUpdateImage label="FW Update Image Build">
        <FWMeRegion label="ME Image">
            <InputFile value="D:\Software Programmer Sept 2025\Bios Software\Flash Image Tool\Flash Image Tool 14.0.60.1790\WIN32\20251214_171950_XM25QH256B\Decomp\ME Sub Partition.bin" label="ME Binary File" help_text="This loads the Embedded Controller binary that will be merged into the FWUpdate image generated by the Intel(R) FIT tool." />
        </FWMeRegion>
        <FWPmcRegion label="PMC Image">
            <MaxLength value="0x14000" label="PMC Max Length" />
            <InputFile value="D:\Software Programmer Sept 2025\Bios Software\Flash Image Tool\Flash Image Tool 14.0.60.1790\WIN32\20251214_171950_XM25QH256B\Decomp\PMC Region.bin" label="PMC Binary File" help_text="This loads the PMC binary that will be merged into the FWUpdate image." />
        </FWPmcRegion>
        <FWOemKmRegion label="OEM KM Image">
            <Enabled value="Enabled" value_list="Disabled,,Enabled" label="OEM KM" help_text="This setting Enables / Disables OEM KM in the FWUpdate image." />
            <MaxLength value="0x1000" label="OEM KM Max Length" />
            <InputFile value="D:\Software Programmer Sept 2025\Bios Software\Flash Image Tool\Flash Image Tool 14.0.60.1790\WIN32\20251214_171950_XM25QH256B\Decomp\OEMP.bin" label="OEM Key Manifest Binary File" help_text="This loads the OEM Key manifest binary merged into the output image generated by the Intel(R) FIT tool." />
        </FWOemKmRegion>
        <FWIshRegion label="ISH Image">
            <Enabled value="Enabled" value_list="Disabled,,Enabled" label="ISH" help_text="This setting Enables / Disables ISH in the FWUpdate image." />
            <MaxLength value="0x40000" label="ISH Max Length" />
            <InputFile value="" label="ISH Binary File" help_text="This loads the ISH binary merged into the output image generated by the Intel(R) FIT tool." />
        </FWIshRegion>
        <FWIunitRegion label="Iunit Image">
            <Enabled value="Enabled" value_list="Disabled,,Enabled" label="Iunit" help_text="This setting Enables / Disables IUNIT in the FWUpdate image." />
            <MaxLength value="0xA000" label="IUnit Max Length" />
            <InputFile value="" label="IUnit Binary File" help_text="This loads the Iuint binary merged into the output image generated by the Intel(R) FIT tool." />
        </FWIunitRegion>
        <FWPchcRegion label="PCHC Image">
            <MaxLength value="0x1000" label="PCH Configuration Max Length" />
            <InputFile value="D:\Software Programmer Sept 2025\Bios Software\Flash Image Tool\Flash Image Tool 14.0.60.1790\WIN32\20251214_171950_XM25QH256B\Decomp\PCH Configuration Region.bin" label="PCH Configuration File" help_text="This loads the PCH Configuration binary merged into the output image generated by the Intel(R) FIT tool." />
        </FWPchcRegion>
    </FWUpdateImage>
</FitData>
